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Verification: Avoid Overly Long Expressions in Specman e Code

teamspecman

When you write your e code, a good practice is to avoid expressions that are "overly long" even though they are completely legal. While there is no hard definition of what constitutes an overly long expression, such long expressions can lead to human errors and parser processing errors.
Very long expressions are hard to read and understand. This also makes them error prone, as an accidental syntax error in the…
- 11 Dec 2012
Digital Design: SPICE Correlation Made Easy by Encounter Timing System (ETS)

MJ Cad

Hello, and welcome to my first blog!
As an application engineer in customer support, I have received quite a few queries on how to do SPICE correlation of timing numbers. This blog is intended to help users understand the flow/methodology for doing SPICE correlation of static timing analysis (STA) timing results using Encounter Timing System (ETS).
As we know, users do correlation of the critical paths in timing analysis…
- 10 Dec 2012
Verification: Update to the Linux Kernel Message System

jasona

A few months ago I wrote an Introduction to the Linux Kernel Message System. As with all software, especially Linux, things get out of date and need updating. The Linux 3.5 kernel contained changes to the kernel message system that are relevant to my...
- 7 Dec 2012
System, PCB, & Package Design : Leverage System Planning to Maximize Performance of Silicon Interposer

TeamAllegro

Recently, an article was published in Chip Scale Review by Cadence product manager Kevin Rinebold talking about maximizing the value of silicon interposer technology using system planning (see page 30). Today’s semiconductor technologies ...
- 6 Dec 2012
System, PCB, & Package Design : What's Good About RF SiP and Data Management? Look to 16.6 and See!

Jerry GenPart

The 16.6 Allegro RF SiP product has 3 major enhancements to improve your productivity.

Read on for more details …

Data Management of Virtuoso SiP Views

In release 16.6, Virtuoso SiP Architect is enhanced to support data management of SiP views through the Virtuoso Library Manager.
To enable this, files generated in the Virtuoso-SiP Layout flow are now generated in the lib:cell:view format. Starting in the 16.6 release…
- 4 Dec 2012
System, PCB, & Package Design : Minimize Your Mouse Clicks in IC Packaging with New Customizable Wire Bond Application Mode in 16.6

Jeff Gallagher

Whether it is reducing mouse clicks, minimizing access to menus, eliminating the need to modify the find filter, or providing direct access to change options panel settings without leaving the canvas, anything that can be done to improve the efficien...
- 4 Dec 2012
Analog/Custom Design: Mixed-Signal Technology Summit in Japan Provides Technology Updates

QiWang

Japan’s semiconductor industry is undergoing a significant change in recent years. We are seeing a shrinking business in SoC development while design and semiconductor companies are trying to focus more on higher profitable and differentiable products like microcontrollers and power management ICs. Most such designs are mixed-signal designs and hence the demand for technologies and innovations in this area is very…
- 29 Nov 2012
Verification: Speed Verification Turnaround by Extending Metric-Driven Verification (MDV) to TLM

Jack Erickson

One of the main benefits of moving the design entry point up in abstraction from RTL to SystemC/TLM is faster verification turnaround. Higher abstraction contains much fewer details, so simulation at that level runs faster and debug is much more prod...
- 28 Nov 2012
System, PCB, & Package Design : What's Good About PCB SI Setup/Audit? 16.6 has Many New Enhancements!

Jerry GenPart

The Allegro PCB SI Signal Setup and Audit commands were introduced in the 16.5 release. Enhancements have been made to these commands in the 16.6 release.
Read on for more details…

Selection of all Components in Component Class Setup

A new top level has been added to the tree display with a label of All Classes. Selecting the All Classes item will cause all of the visible classes and components to be selected:

More…
- 27 Nov 2012
System, PCB, & Package Design : Open Cavity Design Tools for IC Packaging Now Available in 16.6

Jeff Gallagher

In version 16.5 of the Cadence IC package layout tools, we introduced embedded discrete component support. With the 16.6 release, that support has been extended even further. You are now able to define both manual and automatically-managed open ...
- 27 Nov 2012
Verification: New Product: ARM ACE Assertion-Based Verification IP (ABVIP) Available Now

TeamVerify

Preface: on Tuesday December 11 we are giving a free a webinar on "ACE Assertion-Based Dynamic, Formal, and Metric-Driven Verification Techniques with ABVIP". Register today: http://goo.gl/rmBhh
As anyone who has worked with ARM's AMBA 4 AXI^TM Coherency Extensions -- a/k/a the "ACE^TM" protocol -- knows, there are a ton of different configuration options and operational scenarios available to the designer…
- 26 Nov 2012
Analog/Custom Design: SKILL for the Skilled: Part 5, Many Ways to Sum a List

Team SKILL

In the most recent posts of SKILL for the Skilled (see previous post here) we looked at different ways to sum a given list of numbers. The goal of these articles is not really to help you sum lists better, but rather to use a simple problem to demonstrate and compare features of the SKILL++ language.
In this posting of we show yet another implementation of sumlist using an operator which will be new to many readers. While…
- 26 Nov 2012
Verification: Techniques to Boost Incisive Simulation Performance

SumeetAggarwal

Functional verification is the biggest challenge in delivering more complex electronic devices on increasingly aggressive schedules. Every technique for functional verification relies on a fast simulation engine for execution, so performance is of prime importance to all users.
Simulation performance can't be a single number or optimization because each environment is unique in terms of the methodology deployed, the languages…
- 26 Nov 2012
Verification: UVM e vr_ad -- Specman Read/Write Register Enhancements

teamspecman

If you are a Specman vr_ad user, you probably know that register access is implemented using the read_reg / write_reg. For reading/writing a register, you have to
1. Extend a vr_ad_sequence
2. Add a field of the type of the register you want to access
3. In the body() , call the read/write_reg
For example:
extend MAIN vr_ad_sequence {
    !tx_data_reg : VR_AD_TX_DATA vr_ad_reg;
    !tx_mode_reg : VR_AD_TX_MODE vr_ad_reg;
    body() …
- 23 Nov 2012
Verification: Optimizing ARM Based Designs for Low Power using Emulation

fschirrmeister

The month November goes to the Brits, no question. Not only did the James Bond movie Skyfall open, but Santa Clara also experienced somewhat of a "British Invasion" for ARM TechCon in the Santa Clara convention center. To be there properly ...
- 19 Nov 2012
RF Engineering: MMSIM 12.1 SpectreRF -- Preview of Coming nport Attractions! Part 2

Tawna

Greetings,
MMSIM 12.1 contains many new features to aid RF designers. Many of these changes are described in my Part 1 blog post.
I've saved my favorite for last....here's a preview of the changes to the nport component in MMSIM12.1.
1. The Edit Object...
- 19 Nov 2012
Verification: Need e/Specman Expertise ASAP? Free Training and Verification Alliance Partners Are Available Now

teamspecman

Recently an EDA industry observer relayed some Specmaniacs' concerns about satisfying the increasing demand for e/Specman trained verification engineers in Europe and other geographies. Team Specman is seeing this growth too, and here is what we [Cadence] are doing to help:

* First, we have a network of expert e/Specman service providers located around the world (many of which who can support projects in geographies…
- 16 Nov 2012
Digital Design: The Case for the Tiny Testcase

BobD

I often joke with customers that, although I realize they have to work on large designs, I do my best work on designs with just 2 or 3 instances. That's because I'm often trying to replicate an issue they've observed on their design and I'm attempting to reproduce that behavior in a smaller circuit. I've found tiny testcases to be extremely efficient ways to gain quick clarity on tool behaviors which can…
- 16 Nov 2012
Analog/Custom Design: Discussing Mixed Signal -- New On-Line Forum, and 3-Day Training Classes

AndreasLenz

Are you working in the area of mixed signal?
Then you may want to exchange information and experiences with other engineers.
At the Cadence Community, a new Mixed-Signal Design Forum has been launched, providing a place to discuss topics that cross between analog and digital domains.
It doesn't matter if you're just starting with mixed-signal design, or you have a lot of experience. This is a customer-driven forum that…
- 15 Nov 2012
Analog/Custom Design: Cadence Has Significant Presence in ARM TechCon 2012 and Worldwide ARM Technical Symposiums

Sathish Bala

The recently concluded ARM TechCon 2012, the annual event for ARM users (including hardware and software engineers) along with ARM ecosystem partners, was a huge success. Once again, this event showcased the excellent Cadence-ARM partnership that's helping to bring next generation electronic designs to fruition for our customers.
Cadence had a huge presence at ARM TechCon. On the first day (Chip Design Day) Cadence h…
- 14 Nov 2012
Verification: CDNLive paper: High-level Synthesis on Video Processing ASIC

Jack Erickson

The proceedings from the recent CDNLive! event in Israel recently became available, and you can access them with your Cadence.com account login.The paper entitled "High-level Synthesis on Video Processing ASIC" delivered by Yaniv Fais and M...
- 14 Nov 2012
System, PCB, & Package Design : What's Good About APD’s Shape Shorting? You’ll Need the 16.6 Release to See!

Jerry GenPart

In some designsflows, you need to connect two plane shapes on the same net, but on different layers, together with vias in order to improve connectivity. These “shorting” vias are placed in a regular pattern across the overlapping areas of the shape, in such a way as not to interfere with any routing on layers between the two shapes.
The 16.6 Allegro Package Designer (APD) product now provides a mechanism…
- 13 Nov 2012
Digital Design: Transitioning Your LEF-Based EDI System Design Flow to OpenAccess

wally1

The trend of combining analog and digital circuits on a single chip has been growing for several years. More recently I'm seeing more and more designers improve their productivity by transitioning their designs to Open Access (OA) and taking advantage of the interoperability between Virtuoso and the Encounter Digital Implementation (EDI) System. Whether you're performing floorplanning in Virtuoso (schematic-driven…
- 12 Nov 2012
RF Engineering: MMSIM12.1 SpectreRF Preview of Coming Attractions! - Part 1

Tawna

Greetings!
MMSIM 12.1 contains many new features to aid RF designers. Here's a preview of the changes...
Documentation Improvements
The SpectreRF User Guide is being completely rewritten and updated for MMSIM12.1. Check it out - I'm sure you'll really...
- 12 Nov 2012
Verification: Function Level C Interface – New C Interface for Specman

teamspecman

Working with the conventional Specman C language interface has two major disadvantages:
1. There is a tight dependency between the e code and the C code. The user must include the Specman header file which was generated based on the e code. Every minor change in the e code requires regeneration of the header file.
2. The C interface doesn't support calling e TCMs (Time Consuming Methods) from C code.
Let's take a look…
- 6 Nov 2012

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