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Verification: Practical Guide to the UVM for $15 - Virginia, There is a Santa!

Adam Sherer

Wondering what to get the verification engineer on your list? You know, the one with the zealous love of SystemVerilog and UVM? It's the Practical Guide to Adopting the UVM, Second Edition for only $15!
The Practival Guide to the UVM is the most popular source of knowledge for the UVM. The second edition, available since the beginning of 2013, has sold over 3500 copies. Authored by Kathleen Meade and Sharon Rosenbeg…
- 13 Dec 2013
Analog/Custom Design: Support for Low Power Mixed Signal Designs in Virtuoso Schematic-XL

DeveshJain

Why is There a Need for Low Power Solutions?

With an increase in the demand for high-performance, multi-tasking systems-on-chips (SoCs) for communication and computing, the power requirements for these electronic chips have also greatly increased. There has been a surge in the production of portable devices like mobile phones, laptops, tablets, and game boxes that support multiple applications and use various multimedia…
- 10 Dec 2013
System, PCB, & Package Design : Take Your Via Structures from Ordinary to Exceptional with 16.6 IC Packaging Advanced Commands

Jeff Gallagher

Via structures—those reusable patterns of conductor clines and vias designers rely on to maximize their productivity—have a long-standing place in the robust escape routing feature set in the Cadence IC Packaging Tools. Many of us ...
- 5 Dec 2013
SoC and IP: Great Progress with Ethernet Standards Development

ArthurM

The IEEE 802 local area networking standards committee held its plenary meeting in Dallas recently at the Hyatt Regency Hotel. As a historical side, here is a photograph of the Hyatt from Dealey Plaza, the site of Kennedy’s assassination 50 years ago, and also a photograph of the old Texas school book depository from where the shots were fired:

I attended the 802.3 meetings and there was much progress with…
- 2 Dec 2013
Verification: Covering Edges (Part I) – Cool Automation

teamspecman

With random generation, most of the fields are due to be quite well covered. If the field is of a type with a wide space, e.g. address is of 32 bits, then most likely not each and every of the 0xffffffff values will be generated. As verification engineers, we know that bugs tend to hide in the edges. That is - what will happen if the transfer is sent to the last address, to 0xffffffff? The verification environment…
- 2 Dec 2013
Analog/Custom Design: SKILL for the Skilled: SKILL++ hi App Forms

Team SKILL

One way to learn how to use the SKILL++ Object System is by extending an application which already exists. Once you understand how extension by inheritance works, it will be easier to implement SKILL++ applications from the ground up. I.e., if you understand inheritance, you can better architect your application to prepare for it.
This episode of SKILL for the Skilled starts with an existing SKILL++ GUI application…
- 1 Dec 2013
Verification: Accelerating Code Coverage Using Palladium XP Rapid Adoption Kit

SumeetAggarwal

Code coverage is an effective tool in the verification process, giving insights into testing completeness as well as identifying highly active or inactive areas of a design. Collecting code coverage in simulation on large designs can be a very time-c...
- 25 Nov 2013
System, PCB, & Package Design : Optimize Your PCB Decoupling Capacitors and Remain a Person of Integrity

TeamAllegro

How much integrity is too much? If your PCB designs apply one or more decoupling capacitors (decaps) per power pin, then you may have too much integrity - power integrity, that is. Your designs are also more expensive than necessary and your decap mounting structures have vias in areas that could be better applied for signal routing. If you reduce the number of decaps, will you have less integrity? Will your PCB's Power…
- 22 Nov 2013
Analog/Custom Design: SKILL for the Skilled: Simple Testing Macros

Team SKILL

In this post I want to look at an easy way to write simple self-testing code. This includes using the SKILL built-in assert macro and a few other macros which you can derive from it. The assert macro This new macro, assert, was added to SKILL in SKILL version 32. You can find out which version of SKILL you are using with the SKILL function getSkillVersion, which returns a string such as "SKILL32.00"…
- 21 Nov 2013
Verification: High-Level Synthesis Now Spans the Datapath-Control Spectrum

Jack Erickson

When we talk to prospective high-level synthesis (HLS) customers, one of the slides we show is a pie chart that breaks down the types of production designs (that we are aware of) for which customers have used C-to-Silicon Compiler. The current snapsh...
- 20 Nov 2013
System, PCB, & Package Design : Signal Integrity Analysis of Serial Data Channels—A Complete Solution Using Allegro Sigrity

TeamAllegro

Back in the day, when challenged to transfer data faster, we increased the width of the interface from 8 bits to 16 or from 16 to 32 and so on. The wider the bus got, the more challenging timing became. We added strobes for interface lanes to better manage timing, but faster and wider buses added more complexity. Somewhere around 64 bits and 500 MHz (remember PCI-X 533?), we recognized that the trend could not continue…
- 18 Nov 2013
Analog/Custom Design: Virtuosity: 12 Things I Learned in October by Browsing Cadence Online Support

stacyw

Lots of routing, a little AMS, and finishing off with some fun...
Application Notes
1. Constraint Implementation and Validation in interoperability flow
The Mixed Signal Interoperability (MSI) flow allows designers to seamlessly transfer and implement routing constraints from analog to digital designs. This document covers the steps required to apply and implement routing constraints in Encounter and validate these constraints…
- 15 Nov 2013
Digital Design: 11 Things I Learned by Browsing Cadence Online Support

MJ Cad

I guess by now most of us are already familiar with Rapid Adoption Kits (RAKs). These are packages that include a detailed instructional document and a lab database. You can browse all the available materials at https://support.cadence.com/.

Rapid Adoption Kits (RAKs) - The purpose of RAKs is to demonstrate how users can use Cadence tools in their design flows to improve productivity and to maximize the benefits of their…
- 14 Nov 2013
Verification: High-Level Synthesis—What Expertise Is Needed for Micro-Architecture Tradeoffs?

Jack Erickson

My most recent blog post mentioned how utilizing new algorithms together with high-level synthesis can continue to drive innovation in hardware design by balancing power consumption with performance improvements. A great example of this is what...
- 13 Nov 2013
System, PCB, & Package Design : What's Good About Capture’s NetGroup Update? 16.6 Has a Few New Enhancements!

Jerry GenPart

The 16.6 release of OrCAD Capture provides a few enhancements in the area of NetGroups.
NetGroup membership is visible in the schematic and the schematic printout:

You can assign NetGroups through the Alias dialog:

Read on for more details…

Here is an example showing how to make a simple block diagram and using the NetGroup enhancements.
1. Open a design file. Here’s an example of what can be used:

2. Place net…
- 11 Nov 2013
System, PCB, & Package Design : What's Good About FPGA System Planner and Netgroups? 16.6 Has It!

Jerry GenPart

Beginning with the 16.6 SPB release, FPGA System Planner (FSP) can create net groups automatically whenever an interface is instantiated or a protocol is created. These switches control the auto-creation of those net groups. Turning these on builds the net groups as the design is created:

Read on for more details …

The default net group size is 64 signals. Protocols or interfaces with signal groups larger than 64…
- 11 Nov 2013
Verification: Accelerated Code and Functional Coverage Using Palladium XP

SumeetAggarwal

Code coverage is an effective tool in the verification process—giving insights into testing completeness as well as identifying highly active or inactive areas of a design. Collecting code coverage in simulation on large designs can be a ver...
- 10 Nov 2013
Verification: Coverage Unreachability UNR App - Rapid Adoption Kit

SumeetAggarwal

The Cadence Incisive Enterprise Verifier (IEV) team recently developed a self-help training kit - a Rapid Adoption Kit - to help users gain practical experience applying IEV's Coverage Unreachability (UNR) App. The RAK also helps users see the benefits of different approaches, UNR flow with and without initialization. The "Coverage Unreachability UNR App" RAK is now available on Cadence Online …
- 10 Nov 2013
Verification: Generic Dynamic Run-Time Operations with e Reflection, Part 1

teamspecman

Untyped Values and Value Holders
The reflection API in e not only allows you to perform static queries about your code, but it also allows you to perform dynamic operations on your environment at run time. For instance, you can use reflection to examine or modify the value of a field, or even invoke a method, in a generic way. This means that if the specific field or method name is unknown a priori, but you have the reflection…
- 5 Nov 2013
Analog/Custom Design: IC6.1.6 Virtuoso Space-Based Mixed-Signal Router (VSR)

AndreasLenz

Virtuoso Space-Based Router (VSR) is routing solution integrated into the Virtuoso Layout Suite, which provides a comprehensive set of routing features for a variety of layout tasks. One major design task for layout designs is chip/block assembly routing in mixed-signal analog top (AoT) designs.

What's new in Virtuoso IC6.1.6?

VSR routing engines were enhanced to improve routing quality (QoR) and to give better…
- 29 Oct 2013
System, PCB, & Package Design : What's Good About DEHDL’s Variant Editor? 16.6 Has Several New Enhancements!

Jerry GenPart

The recent 16.6 QISR-2 for Allegro Design Entry HDL has new capabilities for the Variant Editor.

Read on for more details…

Dynamic Viewing of Variants in the Schematic Editor

A new toolbar and menus have been added for viewing variants:

All available variants for a design are listed. It’s easy to switch between any of the variants as well as base views. Selecting a variant will lead to the annotation of variant-specific…
- 29 Oct 2013
System, PCB, & Package Design : Turn Spreadsheet Ball Maps into Components in Seconds with 16.6 Cadence APD and SiP

Jeff Gallagher

Many designers use ball maps, or spreadsheets wherein each cell corresponds to a specific pin position in a regular pitch symbol, to document component interfaces, exchange data with other design teams, or even to optimize net assignments. But, just ...
- 24 Oct 2013
System, PCB, & Package Design : What's Good About Allegro PCB Editor ECSets and Ref Des Values? 16.6 Has a Few New Enhancements!

Jerry GenPart

Beginning with the 16.6 Allegro PCB Editor, the environment variable UPDATE_ECSET_REFDES is now the default behavior.

Read on for more details …

Most Electrical Constraint Sets (ECSets) will map based on Reference Designator (RefDes) values. It is sometimes the only thing that is unique for pins in a topology:

In this picture, U21 and U44 have the same SI model and the same pin use. So the only way to differentiate…
- 23 Oct 2013
System, PCB, & Package Design : What's Good About Allegro PCB Editor Embedded Net Name Display? Check Out 16.6!

Jerry GenPart

A new graphical display option in the 16.6 Allegro PCB Editor embeds net names within the cline path, pins, shapes, and flow lines. Useful in just about any PCB application, the display of net names will be extremely valuable for those involved in design reviews or board debug. This feature is enabled by default in all PCB products and does require Open GL to be enabled. The visibility controls for traces, pins, and shapes…
- 15 Oct 2013
System, PCB, & Package Design : Why Does Signal Integrity Analysis Need to be Power Aware?

TeamAllegro

Ever since the I/O Buffer Information Specification (IBIS) committee broke away from the "signal only" mentality and approved the new standard for including power information within the IBIS spec, there has been a lot of buzz in the industry about performing power-aware signal integrity analysis. Effectively this would mean combining both signal and power integrity analysis into one.

But why does it matter?…
- 11 Oct 2013

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