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Last week over 35 power users from over a dozen companies came together for the latest installment of "Club Formal" -- a user group meeting exclusively focused on topics in formal analysis and Assertion-Based Verification (ABV).  This instance of Club Formal featured several papers from Silicon Valley power users on expert-level techniques, as well as highlights of new "verification apps" that are highly automated…

The 16.5 Allegro PCB Editor now has the added ability to accentuate objects and layers in Allegro PCB Editor by providing pattern support.

Read on for more details …

Stipple pattern support is provided through the assign color, highlight and color commands. The assign color command allows you to assign custom stipple patterns to objects in addition to assigning the color and default highlight patterns it currently…

A press release and a blog post caught my attention this week (October 15, 2012), and they have clearly demonstrated Cadence's leadership in 20nm process nodes and mixed-signal solutions. The press release is titled "TSMC Selects Cadence Virtuoso and Encounter Platforms for its 20nm Design Infrastructure, Spanning Custom/Analog, Digital and Mixed-Signal Design." This press release emphasizes that TSMC's…

The 16.5 Allegro Design Workbench (ADW) now supports multiple shopping lists.

In a nutshell, multiple shopping lists support these capabilities:

•    Provide viewing multiple lists from:
–    One or more common list directories
–    One or more other project directories
–    One or more specific files
–    Lists created from an outside source in the proper format can be referenced

•    Functions for:
–…

The approach shown in this post (part 4) will only work in Virtuoso IC 6.1; it depends on features which are…

Every SoC project uses multiple languages. Even if the design itself is purely Verilog RTL, it's likely that you have some PLI-based stimulus. In many cases there are multiple languages in use due to multiple suppliers, globalized teams, multiple abstractions, and more. Integrating e, SystemVerilog, SystemC, and C/C++ into one simulation is basic but insufficient for SoC verification.  The question asked by SoC verification…

[Preface: the upcoming "Club Formal" on October 17 here at the Cadence San Jose campus will also touch on this topic - please join us!]

While it's now common knowledge that there are many benefits to using simulation technology within a metric-driven verification (MDV) flow, as it turns out there are also an equal number of benefits to using formal analysis technology in such a flow as well.  Even better,…

Indexed ports are used to access composite HDL objects in SystemVerilog (SV). Their most frequent use is to access SV multi-dimensional arrays by defining a simple indexed port and accessing the array elements with the port indexes.

Ports in general, and Indexed ports specifically, are static objects that need to be known in the environment build up. Indexed ports were implemented in such a way that each port needs SV…

A recently published AppNote on converting a PADS ASCII file to Allegro PCB Editor has eased the life of many users by providing a step-by-step methodology and appropriate debugging techniques. It also covers various scenarios where Allegro PCB Editor generates errors or warnings during the translation, and explains how to debug errors and obtain a neat board file (.BRD) to be used in Allegro PCB Editor.

The PADS translator…

Prior to the 16.5 release, the search capabilities in Allegro Design Entry HDL (DEHDL) have been quite limited. This has changed in the 16.5 release with the introduction of a new toolbar for page level search and an Advanced Search and Navigate functionality.
 
Read on for more details …

The Page Search option enables you to search for text on the current page. The text can be a symbol text, net name, property or…

In the Allegro PCB SI 16.5 release, static IR drop analysis has been integrated into PDN (power delivery network) analysis, with several new features added, such as current density display and the display of current direction.

Read on for more details …

Analyze Menu

To invoke Static IR Drop analyze, select Analyze > Static IRDrop Analysis at the bottom of the PDN Analysis form:

 

This will open the following window…

I recently came across a Wall Street Journal article,"ARM Chases Bigger Slice of Smaller Chips,"  that provides a very interesting perspective on how ARM is positioned to capture the microcontroller market, which is its next growth area. ARM based microprocessors are clearly dominating the mobile products from smart phones to tablets across Windows, Android and IOS mobile eco-systems. Most of these devices are…

Starting with release 16.5, it is possible to export data from Allegro PCB Editor into PDF files. PDF files are more portable and secure in comparison to .brd files and can be used by customers to share a subset of design data with their vendors who do not need direct access to design data. PDF files can easily be posted on websites and opened within browsers.

Read on for more details …

Basic Information

The PDF…

Please join Team Verify and other design and verification engineers at the next "Club Formal" on the Cadence San Jose campus on Wednesday, October 17 at 11:30am. This free, half-day event (including lunch) is a great opportunity to learn more about general advances in formal analysis and assertion-based verification, and to network with others in your field.  Based on attendee feedback from previous events, we…

Recall the sumlist_1a function

In a previous posting the function sumlist_1a was defined.

(defun sumlist_1a (numbers)
  (let ((sum 0))
    (foreach number numbers
      sum = sum + number)
    sum))

Describing this algorithm in…

Right up there with functional verification, the challenges of low power design and verification present an existential threat to our customers' products, and ultimately their businesses.  Clearly both sides of the low power coin -- reducing generated heat and/or increasing efficiency to make the most of every available joule -- are of primary concern.  But what happens when external, environmental factors conspire…

The 16.5 Allegro Design Workbench (ADW) Flow Manager has been enhanced to provide a more flexible and robust designer experience. It can now be launched in a stand-alone mode, is faster in launching, can open multiple flows, and you can customize it by adding new buttons!

Read on for more details …

Here’s a screenshot of the new Flow Manager:

You can open the last project, and select from a list of last used…

(defun sumlist_1b (numbers)
  (apply plus numbers))

In this posting, (Part 2), we'll look at improving this implementation by using the apply function with more than two arguments to enable handling…