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The 16.5 Allegro Design Workbench (ADW) Flow Manager has been enhanced to provide a more flexible and robust designer experience. It can now be launched in a stand-alone mode, is faster in launching, can open multiple flows, and you can customize it by adding new buttons!

Read on for more details …

Here’s a screenshot of the new Flow Manager:

You can open the last project, and select from a list of last used…

(defun sumlist_1b (numbers)
  (apply plus numbers))

In this posting, (Part 2), we'll look at improving this implementation by using the apply function with more than two arguments to enable handling…

You've placed and routed your design in the Encounter Digital Implementation (EDI) System. It passed Verify Geometry and Verify Connectivity without a violation. Great!

But when you run DRC signoff with your physical verification tool, you have violations related to the routing. What should you do now?

Depending on your situation there are usually two solutions:

1. Fix the violations by hand. This is okay if there are…

Apologies for the long delay between articles (best intentions and all that).  I last left you with an article about how to parameterize and manipulate device properties in your design without having to edit the schematic.  A very handy feature.  So there you are -- creating and matching and ratioing parameters willy-nilly.  You've changed values and defined ranges and run sweeps. 

And now you're wondering--how in the…

I want to show a few of these examples in this blog post (and a few upcoming posts…

In this post, we will discuss the interesting challenge of reset during simulation.

Specman has a very robust implementation of reset during test, which imitates a return to cycle 0. All threads are terminated, the run() method is called again, and evaluation of temporal expressions is restarted. UVM Testflow has the option to go back to any phase, not just to cycle 0, by calling rerun_phase(target phase). When issuing…

So you are developing your verification environment in e, and like everyone else, you've been hearing a lot of buzz surrounding UVM (Universal Verification Methodology). Maybe you would also like to give it a try. The first question that pops in your mind is, "What would it take to migrate from e to UVM e?"

Well, this is a bit of a trick question. The short answer is that if you've adopted eRM in the…

The current Allegro Design Entry HDL (DEHDL) Page Search toolbar works only on the currently opened schematic page. If the scope of the search is different from the current page, then the Advanced Find & Navigate functionality can be used. This new feature also allows you to define the objects which you would like to search for the text.

Read on for more details …

The Find Filter (available from the Page Search…

The 16.5 PCB SI product’s rectangular mesh scheme is used for shapes, cutouts, slots, anti-pads and voids within shapes. The mesh cell size you pre-specify is the maximum cell size ,and the system will automatically adjust/reduce the cell size if necessary. You can ignore the meshing for anti-pads and small shapes/voids through the Preferences settings.

Read on for more details …

Analyze Menu

All analysis…

Even though it's been over 2 months since this year's Design Automation Conference in San Francisco, I am still surprised by the response that metric-driven, mixed-signal verification gets from our design community. Cadence had quite a few customer presentations at the EDA360 Theater at DAC this year. However, there was one presentation titled "Metric Driven Verification Approach for Analog/Mixed Signal IPs" authored…

The use of separate force (F) and sense (S) connections (often referred to as a Kelvin connection) is a common requirement in the PCB design. The separate force (F) and sense (S) connection at the load eliminates any errors resulting from voltage drops in the force lead. The Kelvin Sense connection is routed by separating the sensing signals (S) from the lines, and delivering the power to the load (F). This type of connection…

The 16.5 Allegro Package Design (APD) product has been modified to provide a different type of method to control wire bond settings for groups. It is important to note the differences between these new group settings and the wire bond groups that existed prior to 16.5. In these prior releases, a wire bond had to strictly adhere to a wire bond group, whereby the group defined the characteristics of the wire bond. In contrast…

Luckily I was able to track down my very busy colleague Bin Ju between assignments and interview her about her first-hand observations of what's going on here in Silicon Valley today.  Bin is an expert on formal and assertion-based verification (ABV), so her remarks focus on the trend toward increasing adoption of formal analysis, how users are leveraging "formal apps" to enable rapid adoption of this technology by…

Last week, a favorite customer of mine called me in a panic, just days from tape-out of a large multimedia SoC. After a minor change in their RTL code their Specman testbench started crashing, even though the e code wasn't changed. Could I help?

Knowing that this customer compiles their e code, and that Specman doesn't tend to crash, the first thing I did was to get them to recompile the e code with the debug…

The 16.5 Allegro PCB Router has a couple new improvements I’ll cover today – Embedded Components Support and Route Quality Improvements.

Read on for more details …


Embedded Components Support

This functionality is basically transparent to the Allegro flow designer. The Router will just translate and route these components normally. For standalone users of the Allegro PCB Router, a new syntax has been added…

The 16.5 Allegro PCB Editor release contains several updates to the Graphical User Interface (GUI) to increase your efficiency and productivity in using the product.

Read on for more details...

Status Bar updates

Functional responses can be obtained by clicking fields in the status bar. For example, the field indicating the current subclass can be selected and changed to a new class/subclass. This is a good alternative…

It is not often that an IP provider gets to showcase their IP performance in a real product demo. Those laurels usually end up going to the end product that uses the IP. But a recent Cadence video features our PCI Express (PCIe) Gen 3 core running flawlessly in silicon in a real system.

We thought we would raise some eyebrows since, as of today, there are very few products in the market that utilize the full power of…

Starting from version 12.1, the SimVision Watch Window accommodates Specman watch items together with HDL watch items. Now you can use the same window to inspect all your watches.

Hyperlink support in the SimVision Watch Window is still on its way, so right now Specview is the default for Specman watches. Nevertheless, you are invited to try out the new feature and voice your opinion.

To choose which watch window should…

I mentioned in my first blog one of my roles in customer support is to identify and author knowledge content for Cadence Online Support (https://support.cadence.com/). In this blog post I want to highlight some of the popular Encounter Design Implementation (EDI) System content published in recent months.

If you're not receiving email notifications on the latest Cadence Online Support content, log in to https://support…

Okay, this one is too cool not to share.

The other day a customer and I were trying to understand a tool behavior better so we did what we all do in desperate times: We read the documentation.

As straightforward as "reading the documentation" would seem, I bet no two users of the system interact with documentation the same way. Some people like to bring up "cdnshelp" at the UNIX prompt. Some like to download…

Over the past several years at various EDA trade events, one of the more popular forums have been panel discussions and interviews asking teenagers about the technology in their daily lives.  However, those forums have been comprised of amateurs, whereas in this interview I've secured a professional technology consultant -- Ms. Kristine Bonhoff, a college student by day, and a paid technical coach and volunteer in her…

Verifiers rejoice: R&D has just released all-new Assertion-Based Verification IP (ABVIP) code as part of Cadence's Verification IP (VIP) and SoC Catalog offerings.  Specifically, the ABVIP code in the July 2012 release has been completely re-architected to be: 

• Higher performing for both Incisive formal and simulation engines (with gains from 1.5x to ~ 10x!)
• Simpler to instantiate and configure
• Easier to use with…

In looking over the shoulders of Encounter users over the years I've found there's a bunch of little tips and tricks I use to make interacting with the tool a little easier that aren't necessarily immediately obvious. Here are some of the more common ones I used this week:

1. When navigating an Encounter log file in a text editor, search forward for "<CMD>". Each time a command is executed it's embedded…