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Verification: Video: DVCon 2012 Digital-Mixed Signal (DMS) Expert Neyaz Khan on UVM Mixed Signal (UVM-MS)

jvh3

E-mail reminders for the DVCon 2013 Call For Abstracts prompted me to look through my DVCon 2012 folder -- lo and behold I came across the following video interview. It was shot during the show, but the official approval fell between the cracks and didn't come through until recently. Regardless, the issues raised in the paper that's the subject of the interview (From Spec to Verification Closure: A Case Study…
- 24 Jul 2012
Verification: My Constraint was Ignored – Is it a Tool Bug? – Part 2

teamspecman

In a previous post we showed some cases of user code that can cause ignored constraints, and how to debug that code using the Gen Debugger. In this post, we shall demonstrate another important example -- where the user code violates IntelliGen's coding guidelines.
Incorrectly written constraints can negatively impact aspects such as generation order or input sampling, leading to incorrect or problematic generation.…
- 23 Jul 2012
Digital Design: Capturing and Processing Encounter Console Output with "redirect"

BobD

In my last post I wrote about writing more compact db access scripts with dbGet's expression-based matching. We found all of the high fanout nets in the design which weren't clock nets:
dbGet [dbGet top.nets {.numInputTerms > 16 && .isClock == 0}].name
This writes the name of each net to the console. But how would we write those nets to a file? Say, for example, if we wanted to call optDesign -selected…
- 23 Jul 2012
System, PCB, & Package Design : What's Good About Customer Support AppNotes? They Will Increase Your Productivity!

Jerry GenPart

Our Silicon Package Board (SPB) Customer Support team has initiated a new blog series promoting specific Application Notes (AppNotes) that we believe will help our customers increase their productivity in using our solutions, flows, and products.

Our Customer Support team will review new and existing Cadence Online Support published AppNotes on a periodic basis and select the “Best of the Best” for those we believe will…
- 17 Jul 2012
System, PCB, & Package Design : Customer Support Recommended - Appnote on Increasing Performance in Allegro PCB Editor

Naveen

While working on very large scale Printed Circuit Board (PCB) files that contain a huge stack-up along with thousands of footprints and numerous shapes, the performance of the Allegro PCB Editor plays an important role in getting the board built in time. Below are example statistics for a large scale PCB:
Apart from upgrading the platform hardware to have more RAM, multi-core processor, or a better graphics adapter, there…
- 16 Jul 2012
Verification: UVM Testflow Phase Debugging- Identifying Blocking Activities

teamspecman
UVM Testflow debugging capabilities have been recently enhanced through the addition of more information to the output of the show domain command. In this post, we demonstrate how this information can be used to answer such questions as
1. What domains are in the environment? What units do they contain?
2. What phase is running now?
3. Why are we still in this phase? Which activity is still running, and blocking us from…
- 16 Jul 2012
Analog/Custom Design: Mixed-Signal Gets Clear Message in China

QiWang

While most of my colleagues in the US were taking a nice break during the July 4^th week, a small group of people including me was on the road for a mixed-signal Tech-on-Tour in China. There was some debate internally on whether designers in China would be interested in such a topic. What we had experienced last week was a clear (not mixed) signal from the IC designer community in China that they are hungry for knowledge…
- 10 Jul 2012
Digital Design: Improve Your Productivity With Rapid Adoption Kits (RAKs) for Encounter Digital Implementation (EDI) System and Sign-off Flow

wally1

As you know, Cadence Online Support is your 24/7 site for getting help and resolving issues related to Cadence software. If you are signed up for e-mail notifications, you've noticed new solutions, application notes, videos and other content are added daily. In this blog I want to highlight a new content type called the Rapid Adoption Kit (RAK). This new content type is a packaging of related material to demonstrate how…
- 9 Jul 2012
Verification: Using Flexible Specman License Searches

teamspecman

Until recently, Specman used to look for its licenses in the following strict, hardcoded order:
Either
1. "Incisive Specman Elite"
2. "Incisive Enterprise Simulator"
3. "Incisive Enterprise Verifier"
Or
1. "Incisive Enterprise Simulator"
2. "Incisive Enterprise Verifier"
3. "Incisive Specman Elite"
Starting from Specman 12.1, Specman supports -uselicense and -noie…
- 9 Jul 2012
Verification: Adding Xilinx C Models to the Virtual Platform of the Zynq-7000 EPP

jasona

Today, I have a good article from Henry Von Bank of Posedge Software related to Zynq. Previously, I posted two articles involving Henry including an interview and a HOWTO about verification and virtual platforms.This time Henry covers an of...
- 9 Jul 2012
System, PCB, & Package Design : What's Good About Capture’s CIS INI Settings? Look to SPB16.5 and See!

Jerry GenPart

This week, I'm providing a very short blog. While the content is brief and simple, the positive impact to the Allegro Design Entry CIS usability is high!

The Capture INI (project level) settings are always dynamic, the CIS settings are more or less static and usually do not change after the initial CIS database related setup. You may often need to clear out and reinitialize your Capture INI settings, but may still…
- 6 Jul 2012
Verification: DAC 2012 Video: Dr. Kerstin Eder, University of Bristol, About Her Course on Functional Verification

jvh3

Dr. Kerstin Eder, a Senior Lecturer in the Computer Science department at the University of Bristol, UK, teaches a course on functional verification. In this interview she outlines how the course is structured, what makes for a good verification engineer, and anecdotes of how students are getting snapped up by industry immediately upon graduation.
If the embedded video doesn't play, click here.
Brief digression in…
- 5 Jul 2012
Verification: C-to-Silicon Japan User Group and Ikegami Production Experience

Jack Erickson

We have been seeing some rapid growth in adoption of C-to-Silicon Compiler high-level synthesis. Given that it is a new way of doing design, we have been holding user local groups to get customers together with Cadence people to share experiences, in...
- 3 Jul 2012
Verification: DAC2012: Xilinx Zynq-7000 - From RTL to Success with Emulation

fschirrmeister

It is nice to see when visions get closer to reality. When Cadence announced its vision for the System Development Suite back in 2011, offering a continuum of engines from virtual prototyping through RTL simulation, acceleration and emulation all the...
- 2 Jul 2012
Verification: Video: DAC 2012 Update on AMIQ’s DVT IDE – New RTL Design Work Flow Support

jvh3

Readers of this blog and of Team Specman will recall that Integrated Development Environment (IDE) and verification services provider AMIQ has been in the vanguard of supporting functional verification methodologies and testbench creation for years. The success of verification engineers using AMIQ's "DVT" IDE product has been increasingly noticed by their RTL designer colleagues such that AMIQ is now adding new capabilities…
- 2 Jul 2012
Verification: SystemC TLM-2.0 Virtual Platform Direct Memory Interface (DMI) Performance Impact

jasona

One of the most interesting concepts in SystemC TLM-2.0 is the concept of Direct Memory Interface (DMI). I remember when Mentor Graphics introduced Seamless back in the mid-1990's. Many users were impressed with how fast it could run embedded sof...
- 29 Jun 2012
Verification: DAC 2012: The Top Seven Reasons for using FPGA Based Prototyping

fschirrmeister

John Blyler, Editorial Director at Extension Media, presented in our EDA360 Theatre at DAC 2012 about "ASIC/ASSP Prototyping with FGPAs" and provided an update on his annual survey on this topic. The current 2012 survey is actually currentl...
- 28 Jun 2012
System, PCB, & Package Design : Shocking Rules and Material Remove ESD Risk in Allegro PCB Smartphone Designs

TeamAllegro

Static electricity can send shocks through your body. We have all experienced walking across carpet on a dry day and then touching a metal doorknob. This shock discharge is formally known as Electrostatic Discharge (ESD). ESD can be annoying to us on a dry day or when wearing nylon clothing, but it can be much more serious to electronic devices. When the current associated with what may seem like a harmless shock enters…
- 27 Jun 2012
Verification: DAC 2012 Video: R&D Fellow Mike Stellfox on the Emerging Bottlenecks in SoC System Verification

jvh3

R&D Fellow Mike Stellfox leads a group of trailblazers inside Cadence. Specifically, Mike's group is tasked with moving our most promising prototypes and methodological theories out of their incubators and into production. In this interview on the floor of the Design Automation Conference (DAC 2012), Mike gives a brief snapshot of how innovations in debug automation have moved from the lab to the show floor, and…
- 27 Jun 2012
Verification: DAC 2012: Enabling the Programming of an Extensible Processing Platform

fschirrmeister

We at Cadence have been writing about the virtual prototype associated with the Xilinx Zynq-7000 Extensible Processing Platform (EPP) quite a bit. At the recent Design Automation Conference (DAC) it was our pleasure to welcome Dave Beal from Xilinx i...
- 26 Jun 2012
Verification: High-Level Design and Verification: How Can We Finally Move on From the Forrest Gump Era?

Jack Erickson

Richard Goering wrote an excellent summary of the DAC panel "High Level Synthesis Deployment: Are We Ready?," which can be found here.His conclusion is that we are getting close, and one of the biggest hurdles still to overcome is the skill...
- 26 Jun 2012
Digital Design: EDI System’s get_metric Command Makes Metrics Reporting Quick and Easy

wally1

In this blog post I want to highlight the command get_metric that was introduced in Encounter Digital Implementation (EDI) System 10.1 and enhanced further in version 11. Have you ever tried writing a script to extract information from the log file like run times or timing results? It becomes complicated quite fast when you're trying to capture the desired data, especially if a command is run multiple times. Also, any script…
- 25 Jun 2012
Verification: Video: DAC 2012 Discussion with EET's Brian Fuller on EDA and Video

jvh3

Continuing our conversation on leveraging social media for EDA, at the Design Automation Conference (DAC 2012) I had the honor of interviewing again with EETimes editor Brian Fuller -- this time the focus of the conversation was on video. Specifically we talked about which video formats have proven to be most popular, and which are most effective for delivering complex technical information.

To play the video, click on…
- 25 Jun 2012
Verification: Video: Oski Technology’s Courageous "72 hour Verification Challenge" Using Incisive Enterprise Verifier (IEV)

TeamVerify

I've seen a lot of intriguing promotions over the years, but at DAC 2012 our partners at Oski Technology tackled a truly unique challenge. To show off their formal verification prowess they took an IP block from NVIDIA sight unseen (actually, on Sunday evening before the DAC they received a spec and a 15 minute briefing) and over the course of 72 hours from Sunday at 5pm to Wednesday at 5pm they used Incisive Enterprise…
- 25 Jun 2012
Verification: DAC 2012 Best User Track Paper Review: Deploying Model Checking for Bypass Verification

TeamVerify

Bypass logic verification is a common and difficult challenge for modern VLSI design that arises in the verification of CPU, GPU, and networking ASICs. Get it wrong and/or miss a bug in the bypass logic and whole system can simply freeze.
Fortunately, the 2012 DAC User Track Best Presentation award-winning paper titled "Deploying Model Checking for Bypass Verification" by engineers from Cisco and Oski Technology (full…
- 19 Jun 2012

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