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In addition to the annotated image gallery (click here or on the image), below are some long form comments on particular aspects of this year's Design Automation Conference (DAC 2012).

Verification momentum - I grant that I might be influenced by some amount of selection bias, but I could swear that this year there was way more interest and vendor presence in the functional verification space than at recent DACs.  Our…

As SoC complexity continues to rise, more IP is being utilized, and the quality and completness expected from IP is increasing rapidly. The IP industry needs to change to meet these new expectations, or risk becomming part of the problem they are actually trying to solve.

Martin Lund, Senior Vice President at Cadence, was recently interviewed at DAC2012 by EE Times’ Brian Fuller. Martin laid out a vision for commercial…

There are two ways in e to define an event to be sensitive to a change of value in the simulator:

1. Use simple_port and bind it to the HDL object. Then create an event that will be sensitive to rise/fall/change of that port value with the @sim sampling event:

sig_p : inout simple_port of bit is instance;

keep sig_p.hdl_path() == "sig";

event sig_e is rise/fall/change (sig_p$)@sim;

2. Use an event_port and define…

In the 16.5 Design Entry HDL (DEHDL) release, Object Visibility Layers are introduced. The different objects in DEHDL are now available on different layers and you are provided a toolbar for which the visibility of each of object layer can be controlled. This is similar to displaying layers of objects in Allegro PCB Editor.

Read on for more details …

The different DEHDL object types available are:

1. Components/Sym…

As clock and data frequencies increase and high-speed systems become more densely populated, noise-free power delivery becomes a major challenge for PCB design. When fast switching devices change state simultaneously, power flow ripple propagates through the power delivery system as noise that varies with frequency. This noise can, in turn, disturb surrounding high-speed devices.

To ensure that high-speed systems continue…

Accellera Systems Initiive released the UVM 1.1b on its website June 1 and announced it on the UVM World site here. Cadence is happy to see this latest release maintaining the APIs and backward compatability of the UVM while improving the quality and stability of the SystemVerilog library.

Building on a decade of experience with the methodology, Cadence offers a unique solution for the UVM. You can see more about the unique…

Analog/mixed-signal design is a hot topic at the Design Automation Conference! At DAC 2012 at San Francisco's Moscone Center next week (June 4-7), you can keep up with the latest developments in mixed-signal design methodology, including design, implementation and verification. You will find it is very hard to choose from so many options. Here is a quick guide to presentations, demos and other events Cadence is involved…

Querying the Encounter database with dbGet is typically pretty concise to begin with. But you might not be aware of its support for expression-based matching, which enables even more compact scripting.

Let's take a very simple but common scripting challenge: Finding all of the high fanout nets in the design.

Then let's take this a little further. How would we write a script to find all nets with fanout greater than…

The new era of “Internet Everywhere” creates a whole new spectrum of applications, ranging from health care, automotive, to entertainment and cloud computing, which demand more and more mixed-signal and low power designs.  In fact, mixed-signal applications have become one of the fastest growing segments in the electronics and semiconductor industry.

Traditional mixed-signal designs treat the analog and digital…

Let's assume you are managing a schematic-driven top level design in Virtuoso and you want to import a digital block Verilog netlist into Virtuoso. This is a very common use model in mixed-signal implementation. While the Layout Database is saved in Open Access (OA), the optimized Verilog netlist needs to be imported into Virtuoso.

• Why use CPF?

The Common Power Format (CPF) describes the design power intent for the…

This post isn't directly about tips and tricks for getting the most out of Virtuoso, but it is about a new source of information and hands-on guidance to help you put those tips and tricks into action.

They're called Rapid Adoption Kits, or--to use the obligatory Three Letter Acronym (TLA)--RAKs.

What is a Rapid Adoption Kit?

RAKs are collateral packages for a particular product area or flow which are designed to…

Prior to the 16.0 release, color and visibility (CV) settings of bond wires in Allegro Package Designer were based on the traditional layer model whereby wires were represented as 2-dimensional cline objects that could be colored and made visible or invisible depending on the layer they were on. In 16.0, bond wires were implemented as true 3-dimensional objects in the database, and their CV were set according to their…

In this blog, I will present some tips that can be very useful when you write e macros. We will see which kind of macro we should use for our purposes, and what options we can use to better define our macro.

Let's begin by looking at the following simple example. Assume that you want to define a method that computes an expression of any type and assigns its value to two variables. Because the expression type is unknown…