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Recently the CDNLive! India 2011 best paper award winner, "Complex IP Verification Methodology Using Property Driven Simulation in IEV," was published in TechOnline India.  This is great news for the verification community because the techniques the NVidia authors describe have broad applications beyond the challenging memory controller project that was the subject of the article.  Specifically, this case study…

With the escalating complexity of analog mixed-signal (AMS) chips, increasing digital content in response to new functionality demands, and steady growth of IP blocks into larger and larger SoCs, traditional AMS verification flows are becoming inefficient in handling full chip verification. High-performance digital verification and high accuracy analog verification represented the foundation for traditional AMS verification…

Maximizing the usage of Multi-cut vias by the router is one key to improving yield. And at advanced nodes it is essential step in the flow. So what are the proper settings and flow to use to maximize multi-cut via insertion with NanoRoute? And how do I know if I'm using the latest recommended settings to achieve routing success?

Fortunately, the application note on NanoRoute Recommended Options is available to help…

Speaking of variation -- and isn't everyone these days -- something strikes me in reading about all the powerful and elegant features of corners management and statistical analysis.  After all the simulations are run and the results are presented, unless you've managed to hit a bullseye on the first design you tried (good luck with that), you're probably going to have to change something in the circuit in order…

In the 16.5 release of Design Entry HDL (DEHDL) -- Cadence Online Support access -- the Selection Filter helps the user select one or more type of objects in the schematic. This makes it easier to perform operations like aligning objects, distributing them, or moving them to a specific area on the page. The selected objects can also be placed in a group and then group operations can be executed on them.

This provides…

Address Bus Topology Support

Part of the setup for Bus Analysis in Allegro PCB SI (for Cadence Online Support access click here) is to indicate the strobe or clock net that is to be associated with each bit of the bus being simulated. This process is straightforward for a data, bus but becomes more complicated for an address bus. This is illustrated in the diagram below:

 
 
In this example there are two strobe nets that…

In this video, Senior Architect in Virtuoso R&D Don O'Riordan shares some background information on his DVCon 2012 paper, "PSL/SVA Assertions In SPICE."  Wait, aren't Property Specification Language (PSL) and SystemVerilog Assertions (SVA) digital assertion-based verification (ABV) languages?  Please let Don explain ...

(Click here if the embedded video doesn't play.)

Joe Hupcey III
for Team Veri…

Last week I had the pleasure of meeting dozens of customers at CDNLive! Silicon Valley, and learning from the keynotes, in-depth technical papers, and synchronistic conversations throughout the event.  Below are some highlights and themes that emerged.

Left to right: Keynote speakers Lip-Bu Tan (Cadence), Rick Cassidy (TSMC), Tom Lantzsch (ARM)

Keynote highlights
Two things about the keynotes linger in my mind: first, the…

In an IC package design, it is common for the designer to customize the BGA component, or even the die components (if they are still subject to changes by the IC owner) in order to optimize the package substrate for cost and efficiency. In order to do this, changes to the components and physical symbols representing them in the substrate layout are often necessary. Since the 14.2 release, Cadence IC Packaging physical…

I've seen a lot of intriguing promotions over the years, but at DAC 2012 June 3-7 in San Francisco, our partners at Oski Technology are planning something truly unique.  To show off their formal verification prowess they are challenging anyone to give them a design sight unseen, and over the course of the expo (specifically, starting Sunday, June 3 and ending 5pm Wednesday, June 6) they will deliver results using formal…

I was out in San Jose last week for CDNLive! Silicon Valley 2012 -- our US user's group conference. I feel like we've been on a good run with this conference during the past few years. I'm seeing users return to present papers year after year. And each year we seem to have new users who are inspired to share what they've been working on at a future conference.

Here are three themes I noticed at this year…

Hello, and welcome to my first blog! As an application engineer in customer support I use Encounter Digital Implementation (EDI) System on a daily basis. Each day I see new issues, design challenges and problems customers are trying to solve. I hope to share many of the common and more interesting problems and their solutions through my blog.

One of my roles in customer support is to identify and author knowledge content…

Just a quick post today …

The Allegro Global Route Environment (GRE) has been enhanced in the 16.5 release to support embedded components.

To expand Allegro's usability in the High Density Interconnect (HDI) environment, GRE has been enhanced to understand Embedded Components. This functionality is basically transparent to the designer in an Allegro flow. You just need to design and route normally.

However, there…

In addition to the annotated image gallery (click here or on the image), or the playlist of videos on some of the papers, panels, partner activities, and tutorials ((click here or on the composite image), below are some long form comments on particular aspects of this year's Design & Verification Conference (DVCon) in San Jose this past February 27 through March 1, 2012.

If the gallery doesn't open, click

In this interview Product Engineer Chris Komar recaps the tutorial on formal apps given on Thursday March 1, 2012 at DVCon.  Chris outlines how the "apps" approach can tackle verification challenges that are relatively easy for formal and formal+simulation to solve, and backs this up with some examples (including a low power app introduced at DVCon last year!)

If the video doesn't play, click here

More background…

With the theme of Connect, Share and Inspire, this year's CDNLive! Silicon Valley March 13-14, 2012 will be an exciting forum for Cadence customers to share their most recent chip design successes and learn from each other. Among close to 100 presentations during the packed two day agenda, one area stands out is mixed-signal design. There are more than 10 presentations with specific focuses on mixed-signal design challenges…

Several months ago, I started a 3 part series on Guidelines for Maximizing Speed vs Accuracy for Harmonic Balance simulations.

Just a quick blog today on a new 16.5 Allegro PCB Router enhancement for Staggered Via Rules.

The stagger gap value is defined by rules at the following levels:

• PCB
• Layer
• Class
• Net
• Region

Option Descriptions:

on - turns the rule on.

off - turns the rule off (default)

min_gap - controls the minimum distance between consecutive vias in the pattern.
If min_gap is not specified, a proper samenet bbvia/microvia to samenet bbvia/microvia…

We've had some people joining the forum lately that are either brand-new to Encounter Digital Implementation (EDI) system, or are coming back to it after several years away. I thought it would be a good time to highlight some great tutorials for getting started with EDI.

If you're working with EDI 10, check out this solution page:

    Encounter Digital Implementation (EDI) System 10.1 Tutorial for Beginners

If you're…

Allegro PCB Editor has been enhanced in the 16.5 release with three (3) additional DRC checks and an enhanced DFA utility for a 4th DRC entry, and now allows backdrilling from any layer.

Read on for all the details …

Max Neck Length DRC

Presently, the Max Neck Length constraint is applied on a per-segment basis for CLINEs in a routed design; each segment is measured independently within a necked section and compared…

The China Annual Creativity in Electronics (ACE) Awards was established to recognize individuals, companies and technologies that have made profound impacts in the overall China electronics industry each year. Joining with the industry prestigious names like ARM and TI, Cadence Virtuoso AMS Designer won the 2012 Best EDA product award. Five candidates were nominated for this award including Cadence. The award was presented…