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amsDmv (Analog Mixed Signal Design and Model Validation) is an application integrated in the Cadence Virtuoso GUI flow and it can also be invoked from command line with some feature limitations. amsDmv can be used to compare the simulation restults and design interface (pins) from the DUT with those from the reference design. Therefore users can use amsDmv to validate behavioral models with original transistor level models…

On day-one of the Cadence PCB Signal and Power Integrity Three-Day Event, over 100 professionals gathered in the auditorium at Cadence headquarters eager to learn from Robert Hanson’s presentation on Signal Integrity basics.  The presentation started with the Fundamentals of Signal Integrity and moved on to transmission lines, crosstalk, termination strategies, and concluded with the effects of vias on high speed…

Continuing the series of introducing you to the people that create the tools you use every day, in this video the R&D Architect of Incisive Enterprise Verifier (a/k/a "IEV") Vinaya Singh talks about the advantages of combining formal and simulation technologies, the most common misconceptions people have about mixing the two, and where this technology might go in 5 years time (preview: beyond RTL verification…

A schematic page often contains a large number of different types of objects like parts, pins, buses, wires. Designers often need to perform operations like adding new objects, changing object properties, moving, constructing and deleting objects. All these operations require extensive user interaction with the Capture interface.

With the increasing complexity of designs, the number of objects on a page and pages in a…

OVM users have something new to give thanks for this holiday season -- an update to the OVM Register Package (new link!!). This package is used by novice and advanced users and embodies years of experience gathered through hundreds of SystemVerilog projects.

The Cadence genIES team has been remiss since the demise of the OVM World, which left the OVM community to use OVM_RGM 2.5.  We did try to post to UVM World, but that…

Cadence is pleased to be honored by the OpenText Global Partners Program as their 2011 Connectivity Partner of the Year.  The award is a reflection of the close working relationship that we have had with OpenText over the past several years, providing our mutual customers with the best experiences when using Cadence Virtuoso tool suite with OpenText's ExceedOn Demand product line, which provides remote access to Virtuoso…

Inspired by the positive response to my interview of Formal R&D Distinguished Engineer Alok Jain, while I was in India for CDNLive! I jumped at the opportunity to introduce to this community to more leaders in our R&D organization -- people that directly drive the development of the tools you use every day.  Hence, in this video Incisive Formal R&D team leader Deepak Pant talks about how formal has gone well beyond…

The Allegro Design Workbench (ADW) Configuration Manager application is designed for an administrator to manage the ADW environment including:

• Server / Client Installation Configuration
• Company and Site configuration
• Server status
• Metrics Dashboard

It provides a single location where the ECAD environment can be managed and reported on. In ADW 16.5 the focus has been on:

• Site Management
• Metrics Dashboard

Read on for more details…

The first "Club Formal" event in China was held in Shanghai on Oct. 21 2011, and as you can see in the image gallery below 24 customers from different 6 companies came together to share their general experiences and detailed case studies on formal and assertion-based verification (ABV).  We also took the opportunity to announce and demonstrate some new technologies, share our product roadmap, and learn new requirements…

• In Part 1, we saw the rules of sudoku and a brief introduction to the SKILL++ Object System.
• In Part 2, we started solving the problem top-down by implementing the top level function SkuSolve and agreeing to fill in all the missing pieces incrementally until the program was complete. We also saw how to use hierarchical…

Recently I had the honor of presenting the functional verification roadmap at CDNLive! India in Bangalore.  With the high quality of content and networking, it was easy to see why attendance has increased year-over-year; and why CDNLive India has become the premier conference on the region's engineering community calendar.  The following video montage should give you a flavor of the event (if video does not appear,…

There are several enhancements in the 16.5 System Connectivity Manager (SCM)  / Allegro System Architect (ASA) product that I’ve compiled below that I'm sharing in a brief post this week. Please take advantage of these new 16.5 capabilities.

Refresh Option in File Viewer
We now have the option to 'Refresh' the File Viewer. Right click in File Viewer Window and select – Refresh:

 

Copy Project
This option…

Please join Team Verify and other D&V engineers for one or both of the following free events over the next 2 weeks:

* This coming Tuesday November 8 starting at 11:30am on our San Jose campus, we are holding the next installment of "Club Formal."  The main topics for this event will be abstraction and coverage unreachability methodologies.  Here are more specifics: http://www.cadence.com/cadence/events/Pages…

The Call for Papers for CDNLive! Silicon Valley 2012 is open now through Friday November 11th, 2012. CDNLive! is the Cadence users group conference. It provides an opportunity to present and listen to presentations from folks who use Cadence software to get their jobs done. Next year's conference is being held March 13-14 2012 at the Doubletree San Jose.

I've attended a number of these events in the past, both as a…

This is the second installment in an ongoing series of blog posts that includes an email conversation between Fred and Harry, two fictional mixed-signal engineers, about analog behiavoral modeling. You can read the first installment by clicking here. (NOTE: This blog post was written by Walter Hartong and uploaded by Paul Foster).

Hi Harry,

As I said, this was really the fun stuff. We are coming into the region of 1000x…

I am often asked for guidelines on maximizing speed vs. accuracy for SpectreRF harmonic balance simulations. 

Today, I'll discuss part 2 of the 3 part series consisting of:

• Which Engine:  Spectre or APS?
• Oversample vs Number of Harmonics
• Harmonic Tr...

Due to architectural changes in SPB16.5 Design Entry HDL (DEHDL), we no longer require various modes of operation -- such as Hierarchy mode, Expanded mode and Occurrence Edit mode. There will be no need to change modes while working on the schematic since the explicit need for design net listing and design expansion is removed. This is a HUGE simplification from prior releases!

Read on for more details …

Designs…

Introduction

This is the first of a series of blogs where we will add pieces to the story over time. This is an email conversation between Fred and Harry, two fictional mixed-signal designers, where Fred is adopting various modeling techniques to realize faster simulations while maintaining acceptable levels of accuracy. (NOTE: This blog post was written by Walter Hartong and uploaded by Paul Foster).

How Fred came to mixed…

[Author unknown]

Last week (October 23rd, 2011 or 24th depending on which source you read) we lost Dr. John McCarthy, one of the great contributors to the field of computer science. I'd like to send my condolences and best wishes to friends and family he left behind.

John McCarthy was the 1971 recipient…