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There are currently multiple options for model editing in the Allegro PCB SI environment. These include the legacy dialogs within the PCB SI and SigXplorer environments. Although these dialogs provide graphical editing, they are cascaded through many levels and default to text editing for certain model types. The goal is to provide a single environment for model editing and validation for all applications, and to replace…

All pun-tastic references aside, connecting SystemVerilog and SystemC is becoming a commonplace request.  In most cases, the request is to do this using UVM as the testbench methodology. One of our resident technical experts, Phu Huynh, will lead a webinar on this subject on October 20.

Cadence pioneered efforts to connect a major methodology across multiple languages in 2009 with the release of OVM multi-language support…

In the distributed co-design environment in the SPB16.5 Allegro Package Designer release, a die abstract file is used to convey die information between IC and package layout tools. For ECO purposes, it is imperative to know the changes that are incorporated inside an abstract file before incorporating them in the database. The Component Compare feature in SiP allows you to view differences between die layout information…

(defun SkuSolve (partial_solution)
  (let ((sudoku (SkuInitialize (SkuNew) partial_solution)))
    (printf "starting with: \n%s\n"
            (SkuPrint sudoku))
    (printf "\nfound solution:\n%s\n"
            (SkuPrint (SkuFindSolution sudoku…

Well, here I am embarking on my fifth post in which I point out illogical situations I'm come across in my daily life and suggest that the real world is missing some useful assertions. What started out as a fun way to fill a blog post has turned into a series that has received a lot of positive feedback and, as I mentioned in my most recent post, plenty of page views. I'm beginning to wonder if I'm beating this…

At the Electrical Performance of Electronic Packaging and Systems conference (EPEPS 2011) in San Jose, Calif. Oct. 23-26, Cadence will demonstrate our latest technology developed for PCB multi-gigabit design and analysis. Join the buzz at Table 8 while the exhibits are open on Monday and Tuesday (10/24-10/25), as our product experts will be available to discuss and demonstrate 3D Full-Wave Analysis Technology integrated…

Many designs have multiple independent clock inputs with different frequency specifications and/or different frequency ranges. In simulation based environments we see regressions run with randomly varying clock phase timing parameters to cover the many possible combinations. A simple Verilog example might look like:

initial begin

clk = 0;

      forever #(RANDOM_PERIOD/2) clk = !clk;

end

In the formal world we can also specify the…

With the SPB16.5 release of Allegro Global Route Environment (GRE), you can now prevent “Compact” routing on bundles that don’t need it.

This compact routing functionality was designed to keep the delay patterns as tightly packed as possible as part of a methodology that preserved design space. While this is a good thing, it does tend to increase coupling and crosstalk. Designs where this feature may…

You've just sat through a 2-hour program review.  The 30 minutes you spent describing your sparkling new UVM verification environment were electrifying.  Of course, the hardware and software reviews were boring.  Blah, blah, blah about design trade-offs with some buried references to register APIs.  Your metric-driven verification (MDV) plan completely covers the spec, so you are sitting pretty.  Or are you...

Duolog and…

Greetings,

I am often asked for guidelines on maximizing speed vs. accuracy for SpectreRF harmonic balance simulations.  In a series of 3 blogs, I'll discuss some of the "knobs" that you can tweak, those being:

    * Which Engine:  Spectre or...

High Density Interconnect (HDI) techniques are increasing in the PCB domain. HDI provides the ability to place components on both sides of the board and helps reduce the PCB layer stack. Allegro PCB Router started evolving in this direction from the SPB16.2 version with drill holes and microvias. In the SPB16.3 release, constraints for blind and buried vias, and stacked via enhancements, were provided.

With the SPB16.5…

Everyone can agree that Assertion-Based Verification (ABV) is a powerful methodology for uncovering corner-case bugs, exposing functional coverage holes, and increasing verification observability.  HOWEVER, there is often one teeny-tiny issue that inhibits its wider adoption: hand-writing assertions can be a real pain.  To overcome this obstacle, assertion synthesis technology has emerged that enables rapid proliferation…

I remember when I first started working with the Cooper & Chyan Technology (CCT) router back in the day. It had this great feature where you could darken the display for everything in the design other than what you had selected. This was particularly useful when you were trying to route a net because it focused your eyes on the task at hand while still providing visibility to the rest of the design that you had to avoid…

Imagine you are days away from completing the implementation of a fairly complex mixed-signal design, and you are already day-dreaming about the vacation you have planned in a few weeks. Then it happens -- the dreaded change in the design requiring ECOs to digital or analog content, or worse yet, implementation problems that need fixing. Should you call the travel agent to see if you can still buy travel insurance…

While I understand that a new Kindle Fire at $199 MRSP is significantly more than a dime novel, I assert that today's launch of the new Amazon tablets takes us one step closer to the "paperback computer" becoming a reality.  Here the term paperback computer isn't just a clever play on words regarding the bookish seller of these devices.  Instead, it's a reference to a conjecture introduced in 1992 by the…

When you first start using dbGet, many of your queries branch off the "top" keyword and then traverse to "insts" or "nets". These searches return a list of all the instances or nets in the design. But sometimes it's necessary to query the available cell masters -- some of which may or may not be instantiated.

Common reasons for needing this are for finding things like well taps, end caps…

While assertion callbacks have existed in Specman/e for several years now, several questions on their usage have surfaced recently, so here is a short refresher on their usage.

ABV (Assertion Based Verification) is, more and more, becoming an important aspect of any complete verification.  HDL assertions help to detect more bugs earlier in the process and closer to their source.

This feature enables the integration between…

Prior to the SPB16.5 release, multiple designers can edit and update the same Allegro PCB Designer design without conflict notification. To prevent this situation an advisory lock feature is now available in 16.5.

Read on for more details…

When opening a design for editing, Allegro PCB Designer will generate a lock file (<design>.lck). This lock file is maintained until Allegro PCB Designer exits, opens another design…

Partial Design Simulation aims at unifying the PCB and simulation flow by enabling the designer to use a single schematic for both simulation and PCB implementation. This gives the designer the ability to work with a larger design that may contain portions that will never be simulated in Allegro AMS Simulator, and also allows different circuits (in the design) to be simulated with different simulation profiles.

Using…

The number of licensees for ARM's Cortex-A15 CPU core is growing rapidly, particularly for mobile computing applications.  Customers tell us that's because it provides multiprocessor support and hardware based coherency while consuming only a small amount of power.  In our experience the majority of A15 designs are also adopting the new ACE protocol due to their need for a fast and reliable coherency scheme. 

To…