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The 16.5 release of the Allegro System Connectivity Manager (SCM), also known as Allegro System Architect (ASA), has been enhanced to view implicit power pins in the Component Connectivity Pane (CCP).

This is required for control over the power pins for the design with dies or FPGAs where an ECO is required. This is also required in the co-design flow for SiP where connectivity changes are updated using the ECO Netlist…

Accurate static analysis and complete coverage of the functional space remain very challenging for mixed-signal designs.  The functional verification of mixed -signal designs has never been completely possible.

It is very common to use behavioral models of analog/mixed-signal blocks during the full chip functional verification stage, and to use .lib timing models during the physical implementation stage. There…

All Allegro PCB Editor designers know about the uprev process to migrate PCB .brd files from prior SPB releases to a newer release. The Allegro Design Entry HDL (DEHDL) designers rarely need to uprev. With the 16.5 release, however, you will need to uprev designs.

The 16.5 release includes major architectural changes aimed at providing a Design Aware DEHDL with a dynamic connectivity model. In the new architecture, there…

In Silicon Valley there is a popular fitness program called "Boot Camp" where people volunteer to be run through rigorous exercises by a demanding instructor, analogous to what armies around the world do bring new recruits up to the desired physical fitness standards.  Team Verify has a similar "boot camp" program where we rapidly train engineers in Formal and assertion-based verification (ABV) techniques.…

The N-queens issue is a challenging but standard puzzle when it comes to the world of constraint solving. It's a generalization of the 8-queens puzzle, whose description can be found in detail in Wikipedia (http://en.wikipedia.org/wiki/Eight_queens_puzzle.)  The challenge is to place N queens on an NxN chessboard in such a way that no pair of queens can attack each other.  For those unfamiliar with chess rules, this…

Open solutions are just curiosities until the ecosystem figures out how to turn them into money.  Java and Linux are good examples of that.  When they first hit the "open" space, they were interesting technical solutions to interoperability (Java) and breaking the proprietary operating system monopoly (Linux).  It's only when companies started wrapping products and services around them that they really…

Inspired by Brian Fuller's cross-country "Drive for Innovation", last week I jumped at an opportunity to head out and visit customers in the heartland of America.

Here were the common themes heard during the trip:

(1) Discovering Power People Didn't Know They Already Have
A lot of people don't realize that support for the things they need to do are actually in our products already (in some cases, it's been…

ACE is here. Are you ready?

Designers of multimedia smartphones, tablets, and other mobile computing devices face greater challenges than ever. They have to deliver ever more capable and responsive systems, yet must also consume the least amount of power possible -- certainly no more than their competitors.To achieve these goals, designers have been employing multi-processor architectures for many years. However, the need…

In the previous couple of SKILL for the Skilled postings, we looked at some of the features of SKILL++. In fact, we saw local functions, higher-order functions, and lexical scoping. Still another set of features of SKILL++ is called the SKILL++ Object System. This system provides a standardized way of implementing object oriented SKILL applications.

Object Orientation

An Object System is a programming language…

The following question has come up in comments: "How do I measure F_max for an MOS transistor?" The measurement methodology -- testbench, analysis, calculator setup, stimulus, etc.-- does not change whether you are measuring bipolar transistors...

How many times have you wanted to look at a certain standard cell in the Encounter Digital Implementation (EDI) system, so you go hunting around the design to find one, or use the Design Browser to find one? Then you turn off the nets and special nets to see only the contents of the cell. Or, maybe the cell type you wanted to look at is not even in your netlist currently. Maybe you want to look at an INVX4, but there…

Currently, many of the SPB products support extended nets, better known as Xnets. Xnets are created automatically when a signal model is assigned to a component and that signal model defines that a connection is to be made between two pins of the component. This creates an Xnet that connects the nets that are assigned to these two pins.

When an Xnet is created, all of the electrical constraints on the nets that form the…

I get quite a few questions from designers along the lines of  "How do I set the number of pss/hb harmonics and pnoise/hbnoise sidebands in order to get accurate results?"  Here are some general guidelines that I follow:

Welcome back for Part 2 of a two-part PCI-SIG video demo featuring Cadence’s PCI Express Gen3 Controller IP advanced capabilities, with a discussion on Single Root I/O Virtualization (SR-IOV). Part 1 was covered in a recent blog post.

Many of the problems that customers encounter today when running a signal integrity (SI) analysis tool are caused by the design not being properly set up. The Allegro PCB SI tools require information that is specific to the tool, and it must be available before the tool will function correctly.

Today there is a Setup Advisor command whose purpose is to help you set up the design correctly. Although this command is useful…

In my previous blogs, I talked about productivity enhancing features of Virtuoso Analog Design Environment XL and how designers can take advantage of these capabilities to design complex custom analog ICs. The Virtuoso Analog Design Environment XL multi-test bench environment, specification compliance and statistical analysis tools allow designers to cover the design space in a fast and efficient manner. Compiling and…

This video is part one of a two-part series demonstrating the Cadence PCI Express Gen3 IP silicon on the customer's PC board while it's being tested with a LeCroy Protocol Analyzer and Exerciser.  In part one, Ashwin Matta, Cadence engineering director, discusses the IP performance and core capabilities of the Cadence PCI Express Gen3 IP captured by the display trace.

Highlights:

• The Cadence PCI Express 3.0…