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Cadence Welcomes VLAB Works

Cadence welcomes VLAB Works, a division of Australian Semiconductor Technology Corporation…

Corporate
• less than a min read
Automotive , featured , Virtual Development Environment , vlab , Protium

Time on Your Side: Launching PSS Perspec Composer

We all agree that time is precious. As PSS ( Portable Stimuli Standard ) models get…

OK202502201742
• 3 min read
featured , Perspec , pss , portable stimulus

Cadence Announces Industry's First Verification IP for Embedded USB2v2 (eUSB2v2)

USB Promoter Group has released the eUSB2® Version 2.0 specification (eUSB2v2) in…

Sanjeet Kumar
• less than a min read
Verification IP , eUSB2v2 , featured , Functional Verification , USB
Verification

Latest blogs

High-Bandwidth Memory Evolution from First-Generation HBM to the Latest HBM4

HBM4 is the latest generation of the High Bandwidth Memory (HBM) that has become…

• 3 min read
Verification IP , VIP , JEDEC , HBM , hbm4 , DRAM , High Bandwidth Memory , memory models , HBM3 Vs HBM4 , verification

Verification of PCIe's TDISP for Device Interface Security

The TEE Device Interface Security Protocol (TDISP) is a critical component in ensuring…

• 5 min read
Verification IP , Functional Verification , CXL3.0 , PCIe , TDISP , IDE , verification

An Overview of CXL Mode Alternate Protocol Negotiation

The Peripheral Component Interconnect Express (PCIe) protocol has a very powerful…

• 4 min read
CXL , Verification IP , VIP , PCIe , verification

Evolution of CXL PBR Switch in the CXL Fabric

Compute Express Link (CXL) is a transformative technology that significantly improves…

• 5 min read
Fabric manager , Routing , switch , CXL3.0 , CXL switch , TYPE , SPID , PBR , DPID

UEC-CBFC: Credit-Based Flow Control for Next-Gen Ethernet in AI and HPC

For ages, Ethernet has been the backbone of networking — starting from simple web…

• 2 min read
Verification IP , artificial intelligence , Ethernet VIP , Functional Verification , VIP , UEC , machine learning , Ethernet , Hyperscalers

Training Insight: Unlocking the Power of the Xcelium Logic Simulator

In the fast-paced world of digital design and verification, simulation tools are…

• 1 min read
Xcelium Logic Simulator , Training Insights

Fast Emulation Requires Fast Debug! This Is How It is Done

Introduction Emulation has become a critical tool for verifying complex system-on…

• 3 min read
debug , Palladium , verisium , Emulation , Verisium Debug

Scalable I/O Virtualization: A Deep Dive into PCIe’s Next Gen Virtualization

The demands of modern cloud computing—massive scale, constant agility, and tight…

• 6 min read
Verification IP , Functional Verification , VIP , PCIe

LPDDR6: The Next-Generation LPDDR Device Standard and How It Differs from LPDDR5

Low-power DDR SDRAM has been one of the most widely used memories in the semiconductor…

• 4 min read
Verification IP , LOW POWER DRAM , JEDEC , LPDDR6 Vs LPDDR5 , DRAM , lpddr5 , lpddr5x , memory models , Lpddr6

UEC-LLR: The Future of Loss Recovery in Ethernet for AI and HPC

As Artificial Intelligence (AI) and High-Performance Computing (HPC) systems become…

• 2 min read
Verification IP , artificial intelligence , uvm , LLR , Functional Verification , UEC , Ethernet , HPC , Ethernet UEC , AI/ML

MIPI MPHY 6.0: Enabling Next-Generation UFS Performance

High-speed chip-to-chip data transfer is continuously evolving to meet increasing…

• 1 min read
Verification IP , UniPro , MIPI Alliance , VIP , MIPI , MPHY

Celebrating LPDDR6 Specification Publication: Cadence Hosts JEDEC LPDDR Meeting

Low-power DDR SDRAM is one of the most widely used memories in the semiconductor…

• 2 min read
Verification IP , Design IP , JEDEC , LPDDR PHY IP , DRAM , lpddr5 , LPDDR Controller IP , memory models , Lpddr6

Training Webinar on Protium X3: Using FullVision for Debugging

Join me, Sandeep Nasa, Senior Principal Education Application Engineer, in our free…

• 1 min read

The Evolution of CXL.CacheMem IDE: Insights into CXL3.0 Security Feature

In continuation of our series on IDE blogs, Why IDE Security Technology for PCIe…

• 3 min read
CXL3.0 , VIP , PCIe , verification

Cadence Welcomes VLAB Works

Cadence welcomes VLAB Works, a division of Australian Semiconductor Technology Corporation…

• less than a min read
Automotive , featured , Virtual Development Environment , vlab , Protium , Palladium , xcelium , VDE , helium , System Verification

Insights from the Verification Software Track at CadenceLIVE Silicon Valley 2025

Earlier this month, I had the opportunity to attend CadenceLIVE Silicon Valley 2025…

• 2 min read
Verification IP , SVG , software , cadencelive , SimAI , xcelium , verification

UALink: Powering the Future of AI Compute

On April 25, the UALink Consortium officially released the UALink 200G 1.0 Specification…

• 2 min read
Verification IP , VIP , Ethernet , PCIe , HPC , UALink , AI/ML

eMMC: The Embedded Storage Powering On-Device AI

In today's world of increasingly intelligent devices, efficient and reliable storage…

• 2 min read
Verification IP , VIP , verification

Using PSS Registers with Perspec for Portable Programming Sequences

When you use Cadence’s Perspec System Verifier and the Portable Test and Stimulus…

• 6 min read
Perspec , perspec system verifier , pss

NOP Flit Payload: A Dedicated Debug Channel

Modern PCIe systems are complex, with high-speed data transfer and intricate protocols…

• 3 min read
NOP Flit Payload , debug , PCIe , PCIe 6.0 , PCI Express , Debug Chunk , NOP.Debug Flit Payload

Unlocking Efficient Debugging with the Verisium WaveMiner App

Overview of the Verisium WaveMiner App Verisium WaveMiner is part of the Verisium…

• 2 min read

Training Insights – Tcl Scripting Course for Beginner and Advanced Users

Tcl is a versatile scripting language used in automation, testing, networking, and…

• 1 min read
EDA tools , scripting , tcl

USB4 Port Operations

Designs are tested in the labs for various electrical compliance tests defined in…

• 3 min read
USB4 VIP , USB4v2 , usb4 , USB4 Version 2 , usb4 router

Time on Your Side: Launching PSS Perspec Composer

We all agree that time is precious. As PSS ( Portable Stimuli Standard ) models get…

• 3 min read
featured , Perspec , pss , portable stimulus

Cadence's 2024 Training Programs and Resources

As we welcome 2025, let’s take a moment to reflect on the most viewed blogs and videos…

• 4 min read
onboarding , Functional Verification , RTL , System Design and Verification , Protium , training_byes , SVG , verisium , RAK , blended_training , webinar , digital_badge , ucle , live , ask , xcelium , accelerated , verification

Cadence Announces Industry's First Verification IP for Embedded USB2v2 (eUSB2v2)

USB Promoter Group has released the eUSB2® Version 2.0 specification (eUSB2v2) in…

• less than a min read
Verification IP , eUSB2v2 , featured , Functional Verification , USB , eUSB , eUSB2

AMBA LTI Verification IP for Arm System MMU

The AMBA LTI (Local Translation Interface) defines the point-to-point protocol between…

• 2 min read
amba5 , Verification IP , featured , Address translation , LTI , SMMU , AMBA , DTI , ARM

Understanding Extended Metadata in CXL 3.1: What It Means for Your Systems

As technology continues to advance, so do the ways we connect and manage memory and…

• 3 min read
Verification IP , Memory , CXL3.0 , System Design and Verification , VIP , PCIe , AI/ML , data centers , cloud computing
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