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Prior to the Allegro Package Designer (APD) 16.3 release, Design Rule Check (DRC) markers created by Assembly Rule Checks had to be external DRC markers since no constraint IDs were associated with the ADRC constraints.  In the 16.3 release, Constraint IDs were created for each of the rules. It enabled us to make a change to DRC markers.  For the 16.5 release, each Assembly DRC (ADRC) rule gets its own marker based on constraint…

At DAC I had the honor of being interviewed by EE Times editor Brian Fuller on my experiments with social media to connect to the communities of engineers that use the products and capabilities I help bring to market.  Specifically, I shared with Brian the channels I've seen work well so far, which ones are starting slow but are still promising, and ones which are just not a fit.  We also discuss what the future may…

Are you interested in an automating your directed or random test list that you manually maintain in MS Excel?  Or are you looking to connect your coverage results automatically back onto those tests?  Enterprise Planner, the verification plan creator utility within Incisive Enterprise Manager, can save you 50% of the management overhead associated with keeping track of your tests, and automatically back annotate coverage…

I've seen a few requests in the forums asking about EDI videos. Today I will show you how to find them on the Cadence Support website.

First, go to support.cadence.com. One of the menus across the top is called "Resources". Hover your mouse over this menu and click "Video Library" near the bottom:

On the next page that comes up, click "View all content for all products" in the lower-right:…

This new 16.5 Global Route Environment (GRE) functionality was designed to allow the router to obey plane shapes that are found on signal layers. This is especially useful when a user is trying to work a breakout/route solution and maintain the power integrity of today's high power chips.

This functionality has some ramifications -
    1. It is global in nature. In other words, it cannot be controlled at the bundle level…

I realize that I have been quite remiss in that I have not yet blogged about the new all-singing all-dancing ViVA waveform viewer which was released in IC6.1.5 back in January.  All right, it doesn't really sing and dance -- but would you really want it to?  Really?  Submit an enhancement request and we'll see what we can do...

In the meantime, I can tell you that ViVA (oh, that's Virtuoso Visualization and A…

The creation of behavioral models is only one part of the process of using those models in a mixed-signal design verification flow. If the model and design don't match, the effort is worthless. Even worse, it can damage the entire design verification process.

"Why should I care about keeping my behavioral models and designs in synch ?"

The benefit of using a bottom-up behavioral model to improve…

Ever since Assertion-Driven Simulation (ADS) became available, I have been working with customers to integrate ADS into their standard design and verification flow.  Below are some true stories from my direct experience with ADS out in the wilds of Silicon Valley.

The very first use mode I helped a customer to put together is what I call "Integration Bring Up".  This flow is very applicable to designs with standard…

At the June 2011 PCI-SIG Developer's Conference, Cadence demonstrated Cadence Design IP for PCI Express 3.0 controller IP implemented as a high-performance, dual-mode, 128-bit data-path, x8 PCI Express 3.0 controller configuration in a customer's ASIC. The Cadence PCI Express 3.0 controller in the ASIC reference card was attached to a LeCroy Summit T3-16 analyzer and Summit Z3-16 exerciser platform to demonstrate the…

My colleague and Cadence Distinguished Engineer Mike Stellfox leads a group of trailblazers inside Cadence.  Specifically, Mike's group is tasked with moving our most promising prototypes and methodological theories out of their incubators and into production.  In this interview on the floor of DAC 2011, Mike gives a brief snapshot of the migration to the Universal Verification Methodology (UVM) by customers and EDA…

Designers normally create nets or groups of nets to assign constraints. This leads to nets rules, net class rules, and net class to class rules. As the size of physical symbols (footprints) is reducing, the need for region specific rules is also increasing.

When all these constraints are applied, the amount of memory consumption by the Allegro PCB Router increases. In 16.5, proper use of Net class and Net-class to class…

To complement our support of DAC, CDNLive, and other large-scale events, where the program touches on holistic approaches to whole levels of design and verification realization, Team Verify is also proud to host the "Club Formal" event series.  Patterned after the popular "ClubT" series for Specman users and other Trailblazers, Club Formal is a deep dive exclusively focused on topics in formal analysis and assertion…

I was asked recently about how to easily collect coverage on the sequences generated by the verification environment.  Since this question has come up before, I thought I would take this opportunity to write a short blog on how to quickly and easily collect coverage on generated sequences. 

A comprehensive coverage plan contains coverage of the DUT output, internals, and also the stimuli created and sent by the verification…

How many times have you done this: you want to flip or rotate a cell in your design, so you select it and hit the Q key. The Attribute Editor form pops up, you choose the orientation you want in the Orientation drop-down box, then hit OK or Apply. I know I have done this countless times in my years of chip design.

What if I told you there was a faster, easier way? Well, there is - and it's hidden under the Right Mouse…

One of the key tenants of the EDA360 vision is the need for scalable, correct-by-construction IP creation and integration of design and verification IP.  Duolog is in the vanguard of creating automation to address this challenge, and in this video update Duolog's CTO Dave Murray notes new capabilities with both Cadence and ARM-centric flows, how IP-XACT has become an extensible platform, and how the UVM standard (and…

At DAC 2011 I had the opportunity to reconnect with Yunshan Zhu, the CEO of NextOp Software. After a quick update on their flagship product (BugScope 3.0), Yunshan shares his observations on how assertion synthesis can complement the Universal Verification methodology (UVM), plus he reveals specific application spaces where they have seen BugScope be particularly effective.

If the video fails to play, click here.

Note:…

A couple of blog posts ago, I talked about the worldwide functional verification seminar series that we've been delivering this year. This has been a successful endeavor by almost any metric, but since it's taken a lot of my team's time and energy I'm continuing to monitor every aspect to ensure continued results. Last week I had the good fortune of traveling to Europe for seminars at a hotel in Grenoble and at…

Specmaniacs and IES-XL users around the world know that Integrated Development Environment (IDE) and verification services provider AMIQ has been in the vanguard of supporting eRM, OVM, and now the full production UVM.  At DAC 2011, AMIQ introduced a long awaited feature to DVT for Specmaniacs in particular: direct integration with the Specman debugger.  In this interview shot on the DAC 2011 show floor, AMIQ CEO Cristian…