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In a few short weeks DAC 2012 will be upon us (June 3-7, 2012 in San Francisco, CA), and Team Verify and our colleagues on the Incisive Verification team will be there in force with detailed briefings, panels, papers, posters, and of course live demos in the Cadence booth.  Here are the formal and assertion-based verification (ABV) specific highlights:

* On the show floor Monday June 4 through Wednesday June 6, our main…

Unfortunately, in some occasions, this cup of coffee will be very much needed in order to debug why  Specman managed the memory this way…

This 6 minute video is a quick overview of our formal scoreboard app.  Specifically, the video references the same AXI bridge example included with Incisive Formal Verifier (IFV) and Incisive Enterprise Verifier (IEV) so you can follow along on your workstation!

If video does not open, click here. 

If you want even more background on this app, I invite you to watch the webinar recording on this topic, "Quickly Find Data Transport…

More high-density interconnect (HDI) improvements including the tuning of the auto-router (Allegro PCB Router - SPECCTRA) to use the via patterns, alignment of via list priority with Allegro PCB Editor, and creation and removal of anti-acid bars are available in the 16.5 release of the Allegro PCB Router.

Read on for more details…

In this release, the SPECCTRA auto-router provides the ability to use inset/tangency…

Over fifty PCB enthusiasts ascended upon the Cadence campus in Austin, Texas last month where they were greeted by world renowned signal integrity educator Robert Hanson.  Robert spent two full days taking them from the basics of transmission line theory all the way through the challenging aspects of compliance of serial interface standards running at 8 gigabits per second.  And if that was not enough, he then went into…

Mixed-signal applications are among the fastest growing segments in the electronics and semiconductor industry. Applications in mobile communication, networking, power management, automotive, medical, imaging, safety and security require a very high integration of analog and digital functionality at system, SoC and IP levels.

Unfortunately, compared with the advancement of digital designs over the past decade, the state…

New to the 16.5 release of Allegro PCB Editor is the ability to establish via patterns during group routing.

Group Routing Review

The Allegro PCB Editor supports interactive group routing. Interactive group routing is the routing of more than one net concurrently. You can use this feature when routing a bus with traces that follow the same path and have common physical and electrical rules. To specify the nets for group…

The OrCAD Capture 16.5 release now has a method to generate a report (in CSV or HTML format) for the results from the Find command.

Read on for more details…

After you execute the Find command on a design, you can generate a report (in CSV or HTML format) for the results from the Find command. If you run the Find command to search for different types of objects in a design, the search results will display in different…

The 16.5 release of Allegro Design Workbench (ADW) provides support for generic models. As you’ve seen in prior releases, ADW supports the typical Cadence SPB front-to-back models – symbols, footprints, etc. Now, we offer generic model support so you can construct new custom models like PSpice, IBIS and other simulation models.

Read on for more details …

We’ll illustrate the highlights of constructing…

In Specman you would usually see something like:

*** Error: OS signal 11 (segmentation violation) received

       See the stack trace in ./specman.err

To debug:

---------

o Rerun the same test with the same seed in interpreted mode, after

   setting "break on error". Load also any previously compiled modules.

   ** One user module is…

With some notable exceptions, too often technology trade press reporting has been as dour as the general world news.  However, to EETimes editor Brian Fuller, this negativity was at odds with the inspiring technological advances that were regularly crossing his assignments desk.  In a nutshell, Brian's confusion over this dichotomy was the seed crystal behind the "Drive for Innovation" -- a partnership between Avnet Express…

Recently the CDNLive! India 2011 best paper award winner, "Complex IP Verification Methodology Using Property Driven Simulation in IEV," was published in TechOnline India.  This is great news for the verification community because the techniques the NVidia authors describe have broad applications beyond the challenging memory controller project that was the subject of the article.  Specifically, this case study…

With the escalating complexity of analog mixed-signal (AMS) chips, increasing digital content in response to new functionality demands, and steady growth of IP blocks into larger and larger SoCs, traditional AMS verification flows are becoming inefficient in handling full chip verification. High-performance digital verification and high accuracy analog verification represented the foundation for traditional AMS verification…

Maximizing the usage of Multi-cut vias by the router is one key to improving yield. And at advanced nodes it is essential step in the flow. So what are the proper settings and flow to use to maximize multi-cut via insertion with NanoRoute? And how do I know if I'm using the latest recommended settings to achieve routing success?

Fortunately, the application note on NanoRoute Recommended Options is available to help…

Speaking of variation -- and isn't everyone these days -- something strikes me in reading about all the powerful and elegant features of corners management and statistical analysis.  After all the simulations are run and the results are presented, unless you've managed to hit a bullseye on the first design you tried (good luck with that), you're probably going to have to change something in the circuit in order…

In the 16.5 release of Design Entry HDL (DEHDL) -- Cadence Online Support access -- the Selection Filter helps the user select one or more type of objects in the schematic. This makes it easier to perform operations like aligning objects, distributing them, or moving them to a specific area on the page. The selected objects can also be placed in a group and then group operations can be executed on them.

This provides…

Address Bus Topology Support

Part of the setup for Bus Analysis in Allegro PCB SI (for Cadence Online Support access click here) is to indicate the strobe or clock net that is to be associated with each bit of the bus being simulated. This process is straightforward for a data, bus but becomes more complicated for an address bus. This is illustrated in the diagram below:

 
 
In this example there are two strobe nets that…

In this video, Senior Architect in Virtuoso R&D Don O'Riordan shares some background information on his DVCon 2012 paper, "PSL/SVA Assertions In SPICE."  Wait, aren't Property Specification Language (PSL) and SystemVerilog Assertions (SVA) digital assertion-based verification (ABV) languages?  Please let Don explain ...

(Click here if the embedded video doesn't play.)

Joe Hupcey III
for Team Veri…