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With the Allegro PCB Editor SPB16.5 release we've enhanced the existing Allegro drafting dimensioning capabilities, so that when a dimension is created involving one or more design database objects the dimension will subsequently remain internally ‘associated’ with those objects as well. Subsequent editing operations such as the moving of an object can then appropriately and automatically update as required any dimensions…

Wireless, networking, storage, computing and FPGA applications have been moving aggressively to advanced process nodes to take advantage of lower power consumption, improved performance and area reduction. Today, most of these applications integrate a significant amount of analog/mixed signal (AMS) or RF together with digital circuits. Since AMS often occupies over 50% of the chip area, applying traditional, conservative…

In addition to the annotated image gallery (click here or on the image), below are some long form comments on particular aspects of this year's Design Automation Conference (DAC).

Cloud computing - the title of Richard Goering's report on this panel captured the discussion perfectly, "DAC Panel Says ‘Yes' to EDA in the Cloud -- But Differs on When".  Of course there are a variety of private and…

How many times while working in Encounter Digital Implementation system have you wanted to find the transition time on a certain pin? How did you go about finding it? Here are some ways I know that I've used:

• If I knew the pin was failing the max_transition constraint, hunt it down in the .tran violation report.
• Try to find the pin somewhere in my timing reports and look at the slew column.
• Use (gasp!) undocumented commands…

Getting a complex mixed-signal design assembled and completely analyzed for mask design is a huge challenge today. The IPs are complex and too many decisions need to be made to meet design budgets. All this is not possible with anything less than a fully automated, front-to-back mixed-signal design solution.

On top of mixed-signal complexity, battery operated wireless and hand-held mobile applications are extremely sensitive…

I was at the Design Automation Conference (DAC) last week showcasing our latest, greatest Incisive Enterprise Simulator (IES) performance features in the demo suites.  In my "off" time, I was in our DAC booth meeting customers and discussing our advanced verification solutions.  I ran into a long-time SystemVerilog user who had been using that language since the AVM methodology days years ago.  He mentioned to…

In my last blog, Virtuoso Analog Design Environment XL - Embrace the Productivity, I wrote about Virtuoso Analog Design Environment XL's multi-test bench environment and how design teams can make use of this feature to increase productivity and use hardware resources efficiently. In this blog, I will focus on advanced Virtuoso Analog Design Environment XL features like corners analysis and Monte Carlo analysis.

Corners…

In this interview, members of the Texas Instrument wireless group talk about the characterization effort initiated and completed last year between Cadence and IBM using TI RF designs as a pilot. The goal between the two teams was to optimize SpectreRF...

The Allegro 16.5 release was made available on May 17, 2011!

This release adds additional improvements and efficiencies to your design process.

New technologies in Allegro 16.5 include advanced miniaturization capabilities, integrated power delivery network analysis, DDR3 design-in kit, bolstered co-design featured and flexible team-design enablement to address global designer productivity.

Today, I’ll discuss the enhancements…

Last week was the 48^th Design Automation Conference (DAC), held in lovely San Diego. This was the 24^th DAC in a row I've attended, which sounds impressive although I have a number of colleagues who go back even further. This year's attendance was significantly higher than last year's by just about every metric, not surprisingly since the economy has picked up a bit and San Diego is more of a draw than Anaheim…

The 20nm roadmap.  TSMC reference flow 12.  The UVM 1.1 release. Verification IP for ARM ACE.  Assertion-driven simulation.  All of these important items were key EDA360 deliverables this DAC.  Yet there was one thing that I dare say was the most anticipated part of the whole conference: of course, I'm referring to "The Denali Party".  Indeed, the #1 FAQ since Cadence's landmark acquisition of Denali last year was…

In response to the OrCAD and Allegro 16.5 product release, and the growing demand for easy to use and affordable Signal Integrity solutions such as OrCAD PCB SI, TeamOrCAD, TeamAllegro and Signal Integrity expert Robert Hanson will join forces the week of June 20 in Chelmsford, MA.

Cadence has opened up their training facilities to Robert Hanson to teach his popular SI/PI/EMC training courses.  On June 20-24, engineers…

Understandably, EDA industry observer John Cooley had to edit down all the submissions to his annual DAC "Cheesy Must See List".  Unfortunately, the entry for Incisive Enterprise Manager ended up in the wrong spot, and with too short a description to really understand it.  So below is what you want to know about Incisive Enterprise Manager.  Hope to see you in San Diego!

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YOUR COMPANY: Cadence

YOUR TOOL: Incisive…

Understandably, EDA industry observer John Cooley had to edit down all the submissions to his annual DAC "Cheesy Must See List".  Hence, allow us to share the complete text that we submitted for Incisive Enterprise Verifier's Assertion-Driven Simulation capability.  Hope to see you in San Diego!

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YOUR COMPANY: Cadence

YOUR TOOL: Incisive Formal Verifier and Incisive Enterprise Verifier

WHAT TOOL DOES: Formal…

While Assertion-Based Verification (ABV) has been around for many years, ABV has largely been a passive exercise.  For example, assertions can monitor behavior in a simulation environment, model a formal analysis environment with constraints, or provide targets for formal proofs as checks or covers.  This is all very useful and good.  However, assertions are passive objects in these cases.  This means that in simulation you…

In this posting, I continue looking at applications of SKILL++. In particular, I'll also discuss how to create functions that hold onto their state. I'll use these functions to implement multiple-criteria (cascading) sort predicates. I'll look at ways to sort layout pins counter-clockwise around the center point of the design.

 In the previous posting we looked at an implementation of ge…

Talk about stability -- OVM 2.1.1 has had 18 months as the core of Accellera's UVM and accumulated only 13 bugs.  Not too shabby!  With the OVM community preparing to migrate, Cadence and Mentor have posted a bug-fix update -- OVM 2.1.2 -- to OVMWorld to help you get ready to move to the UVM.

As you may have seen in my twitter feed, I've been out talking to customers a lot lately.  Both OVM and VMM users have been…

The Allegro 16.5 release was made available on May 17, 2011!

This release adds additional improvements and efficiencies to your design process.

New technologies in Allegro 16.5 include advanced miniaturization capabilities, integrated power delivery network analysis, DDR3 design-in kit, bolstered co-design featured and flexible team-design enablement to address global designer productivity.

You can read Richard Goering’s…

A new thing that we're seeing with some 45nm libraries is the rule that single-wide filler cells should not be used. At first, this may seem like a difficult thing to ensure in your design flow, but Encounter Digital Implementation system has the ability to handle this. You just have to know the right settings -- and today you'll learn them in five minutes or less.

First, we need to tell the placer that we don…

“You’re only as good as your last product …”

We have been talking about low power simulation and the Common Power Format (CPF) for five or six years now. It’s become popular in most digital designs thanks to a mature methodology and design flow. However, more and more SoC designs are coming up with mixed-signal content. How will low power technologies and formats be used in mixed-signal design?