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Every once in a while, I like to do a lightweight blog post linking my work world of functional verification with the real world. Regular readers may recall my series explaining MDV using quotes from classic Hollywood movies. Today I pose a question: if you had assertions available in your everyday life, where would you use them? Yes, it's a nerdy way of thinking but it's not as if I actually go around saying to…

Last week teammate Adam Sherer and I had the honor of representing the Incisive functional verification platform at the annual CDNLive for Europe, the Middle East and Africa (EMEA) in Munich, Germany.  Among our tasks was to deliver the annual verification roadmap update; support numerous techtorials, demos, and papers; and of course meet with customers and partners.  Along the way I couldn't resist taking a few pictures…

Hi, and welcome back to another Five-Minute Tutorial! Yes, I know it's been a while, but like most of you out there, I'm an ASIC designer, and you know how busy work can get. (Blogging is not my day job, but I enjoy doing it when I have some extra time!)

Today's topic is how to set up your clock routing rules in Encounter. This is best done in the .ctstch file, so that your clocks are routed the way you want from…

As consumers we are very familiar with product miniaturization trends. We demand more functionality in smaller sizes that have longer battery life all the time. The electronics market has been delivering to those customer expectations not just in consumer electronics marketplace, but in all market segments.

Allow us to shamelessly promote a free webinar (including a live demo) this Thursday May 12 at 10am-11am Pacific time, entitled "Verification 1-2-3 with Assertion-Driven Simulation".   In a nutshell, in this webinar Solutions Architect Chris Komar and Product Management Director Joe Hupcey III of Team Verify will show a new approach using both formal and dynamic simulation technologies to increase bug detection…

In my last blog, Virtuoso IC 5.1.41 was Good but Virtuoso IC6.1 is Better, I wrote about the improvements in Open Access, SKILL and Virtuoso Schematic Editor in Virtuoso IC 6.1. In this blog, I am going to focus on Virtuoso Analog Design Environment, mainly on Virtuoso Analog Design Environment XL, its design analysis and verification capabilities, and how design teams can take advantage of these features to increase…

In the previous couple of SKILL for the Skilled postings we looked at some of the features of SKILL++. In fact, we saw local functions, higher-order functions, and lexical scoping. In this episode of SKILL for the Skilled I would like to show a few more practical examples of these concepts.

Functions are first class

In the SKILL language, functions are themselves first class objects. They can be created dynamically…

Attendees of DesignCon 2011 received a sneak peek, and now Allegro PCB designers can officially check out a new power delivery network (PDN) analysis solution as part of the Allegro 16.5 release.  Accurate, flexible, and highly integrated, Allegro PCB Power Delivery Network Analysis provides a unique design and analysis solution.  With no translation of PCB designs required, users of either Allegro PCB SI or Allegro PCB…

Attendees of the Silicon Valley DVClub this past Tuesday were treated to some real life case studies of new tools that help D&V engineers rapidly create assertions (a full report on this event by Richard Goering is posted here) .  As it turns out, one of these case studies -- the presentation by Jing Lee of Broadcom on NextOp's BugScope tool -- had its origin in a poster session presented at DVCon 2011.  I had the…

After a long break, I'm going to try to venture back into the blogosphere, starting off nice and easy--by cheating...

You see, Virtuoso IC 6.1.5 came out at the end of January, and one of the changes made to the Schematic Editor is that many of the handy dockable assistants featured in IC 6.1 are now available at the basic L tier of software.  If you don't know what that means, don't worry, because what I'm trying to…

Allegro 16.5 is another step forward for Cadence towards the realization of the EDA360 vision. Part of that vision is System-on-Chip (SoC) Realization, and SoC Realization requires a broad-based, comprehensive solution for memory and storage IP. 

Because applications used on all types of handheld, desktop, and rack mounted platforms require faster access to data, memory interfaces are key elements for delivering on the…

In my last post, I described three different types of automatic assertions: those derived from the design, those derived from the design with some assumptions such as naming conventions, and those derived from the design plus supplemental files expressing some aspect of design intent. I finished by mentioning the approach taken by NextOp, which analyzes simulation traces to "learn" about a design's behavior…

Just in time for Easter, Team Verify's Apurva Kalia, Manu Chopra, and Suman Ray of the Incisive R&D team created a Rubik's Cube solving Lego robot.  However, unlike other such 'bots (recall the now famous ARM-driven Rubik's Cube ‘bot at ARM's TechCon), the brain of this one is actually a single SVA assertion that is solved in an instant by Incisive Formal Verifier (IFV).  Check it out:

If video…

The answer is "yes, you must initialize it" but the reason may be surprising to many people: DRAM contents are not lost when the power is turned…

There are a couple quick new SPB16.3 Allegro PCB Editor features to mention this week.

Flip Design

Viewing a layout from the bottom side is now available through the flipdesign (View — Flip Design) command or flip icon . The design is flipped about the Y axis.

A true bottom side view from a CAD system is essential when debugging a board in the lab or probing on the manufacturing floor. Design editing can also be done…

I have had a lot of discussions recently around improving the final integration of analog IP. There has been a lot of material published over the years to aid in this task, and I wanted to point to some of my favorites while talking about what has and has not changed.

There is a lot to be learned from digital verification methodologies applied to "big A" mixed signal designs, and the first is leveraging a systematic…

Mixed-signal verification has been one of the hottest topics in the past year, and it was very evident in DVCon 2011, looking at the number of technical papers submitted on this topic. Engineers are looking for solutions to solve tough problems in this space, and the creativity put into developing custom solutions is mind blowing. We are at an interesting stage where engineer's minds are racing past the capabilities of…

If you have defined relational fields in your Allegro Design Entry CIS configuration, you can now include the relation fields in your CIS Bill Materials. When you include relational data in your reports, you can also decide how you want this data displayed. So you can choose to display the relational data horizontally (in the same row) or vertically (one line item per related data).

A completely different perspective…

With the recent release of unified custom/analog flow that is based on the latest version of the Virtuoso IC 6.1.5 technologies (see Virtuoso IC 6.1.5 press release here), it is time to revisit the strengths of Virtuoso IC 6.1 platform and find out how new capabilities enable designers with the productivity gains they have been clamoring for.

Open Access and SKILL

One of the major changes in Virtuoso IC 6.1 is the database…