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In the previous SKILL for the Skilled postings, we looked at a pretty good algorithm for solving the Sudoku puzzle. This algorithm is able to find at least one solution of the puzzle if one exists, and is able to detect that no solution exists if that is in fact the case. In this article we look at a particularly difficult case which the algorithm we have chosen performs poorly.

What about a difficult puzzle?

In his article…

In Virtuoso IC 6.1.5 ISR6, we released a new feature in ADE XL, which had been requested by many customers--the ability to define a measurement expression which operates on the results of another measurement expression across corners.  For example, I can create an expression to measure, say, a delay.  Call it "myDelay".  Now I can create another expression which calculates, for example, the maximum value of "myDelay…

Today's tutorial could probably be called a One-Minute Tutorial, since it's so quick. This is something that came across our internal expert alias, and I figured it's something that most people may not know about. Did you know that you can change the background color of your Encounter Digital Implementation (EDI) design window?

Here's how. In your EDI session, enter the following command:

    setLayerPreference…

In the 16.5 release, all connectivity changes are stored in the hierarchical block directly in Design Entry HDL (DEHDL). Connectivity changes are basically additions or modifications of components, nets, and pin-net connections. The behavior remains the same as in the pre-16.5 release.

Property changes can be stored directly in the hierarchical block on which the object exists, or at the root (top) level design in context…

In release 16.0, the concept of Application Modes was introduced. These application modes are used to set up the tool for specific tasks. The existing applications are General Edit, Etch Edit, and Placement. In 16.5, the Signal Integrity (SI) application mode has been added to be used for high-speed related tasks.

An Application Mode is a “super command” telling Allegro the general function area the user will…

Its’ all about RTL simulation.  I mean gates.  I mean turn-around-time.  Project-level productivity.  Mixed-signal.  Low-power. UVM.  And. And. And. … And the reality is that advanced node SoCs are so complex that it is truly about all of these.  Our new white paper details a systematic approach to verification performance you can use immediately at all levels from core simulation to advanced technologies and methodologies…

One of the big buzzwords around the EDA world these days is "variation."  Don't you just love buzzwords?  Take a perfectly normal, slightly ambiguous word, capitalize it, add a another slightly ambiguous hyphenated suffix, and suddenly you've just solved a new problem for your customers.  "Interface-driven'' "user-centric'', "platform-based" and "variation-aware."…

[Preface: recall the melody of the Buggles' 1979 hit "Video Killed the Radio Star" as you read the following]

Q: What is your favorite pastime?

A: Reading reference manuals!

No?  Really?

OK -- with all due respect to our Tech Pubs team, virtually no one wants to sit down and read reference manuals if they can help it.  And in a perfect world, it should not be required in the first place.  Alas, our world…

Much like Charles Duell's famous 1899 quote**, the notion that the Universal Verification Methodology (UVM) is the be-all and end-all of verification methodology is an urban legend.  The new Advanced Verification Topics book dispells this myth with five topics that describe methodology layers that build on the UVM to serve the requirements of advanced node SoCs.

The Accellera Systems Initiative UVM is gaining great…

Have you ever had a situation where you want to compare two (or more) different areas of a design, so you end up zooming in to one area, then to the other area, then back and forth as you look at various objects and layers, trying to recall the differences? Have you ever brought up two separate Encounter Digital Implementation (EDI) sessions to make this easier? Then today's tutorial is for you!

There is a way to bring…

Right before the December holidays it was my privilege to host the first "Club Formal" here in the U.K.  My colleagues and I welcomed over 20 power users from 8 different companies, providing an exciting diversity of ideas and applications.  We also took the opportunity to sneak preview some new technologies, share our product roadmap, and discuss new requirements from the attendees to better align our R&D development…

In System in Package (SiP) 16.3, the co-design die flow introduced the distributed co-design flow concept, where there is no direct interaction with I/O Planner. Die information flowing between Encounter and SiP Layout is done via a die abstract.  In flows up through 16.3, you first need to load the LEF files for the cell library used by the IC design into the LEF Library Manager and create the Condensed Macro Library…

The 16.5 Global Route Environment (GRE) now allows or prohibits tuning in constraint regions.

This functionality was designed to help PCB designers prevent delay routing in constraint regions. This is generally desirable as the space is so tight in the BGA via field that there is little room and what little there is -- is needed for routing. In addition to a space problem, the vias break up the plane with a lot of voids…

I know we're over halfway through January already (where does the time go?), but Happy New Year everyone! I hope 2012 is a good one for your business and your chip designs, and let's hope the Mayans just ran out of ink when they were finishing the calendar for this year.

Today I'd like to highlight an option of the assignPtnPin command that was added in Encounter Digital Implementation System (EDI) 10.1. This option…

For years now consumer electronics have driven (nay, saved) the EDA industry.  Hence, many events at last week's annual Consumer Electronics Show (CES) in Las Vegas can be extrapolated as leading indicators for the EDA business.  While I couldn't personally attend CES this year, I had two trusted agents (specifically, Unified Communications (UC) expert David Danto of Dimension Data, and Joseph Hupcey Jr., video…

Some of you may remember the blog written several years ago "Shhhhh...SpectreRF Tutorials and AppNotes - One of Our Best Kept Secrets".

Well, the more things change...the more things stay the same!   The location of these tutorials and appNotes...

Another high density interconnect (HDI) technology that has gained popularity is inset vias. The 16.5 release has provided new commands added in Allegro PCB Router to support inset vias.

Via in Pad pattern has been very popular due to its clear advantage of offering lower parasitics as compared to other fan-out patterns like dog bone patterns. But, it may pose a challenge for the assembler to deal with the trapped air…

Continuing the series of introducing you to the people that create the tools you use every day, in this video I ask Bob Kurshan, Cadence Fellow and R&D leader of the Incisive Formal Verifier ("IFV") "Engines Team," about the challenges and/or tradeoffs in creating a formal engine, how to avoid gotchas in tricky problems like cache coherency verification, and how formal technology might evolve over the next…

The 16.5 Allegro PCB Editor release adds differential pair phase tuning as an alternative to using the mouse guided delay tune command, and also quality improvements for transitions at region boundaries.

I’m providing a quick summary this week of these enhancements.

Differential Pair phase tuning

Phase Tuning is an alternative to using the mouse guided delay tune command and offers the precision of finite length adjustment…

Happy New Year!

After many requests, I set aside some time and updated the Using the nport in Spectre and SpectreRF Simulations appNote for MMSIM 11.1.   You may download the appNote on Cadence Online Support.   More nport enhancements are planned, so stay...