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When two users report the same issue in the same week I'm glad I can share the problem and solution via this blog.

I know a lot of you work in an environment where you request computing resources via "bsub." In many cases it's frowned upon to request an xterm to launch jobs and it's preferred to start an interactive session with something like "bsub -I encounter." What we were seeing was that command line navigation…

As a complete gadget geek, it’s always exciting to play with the latest technological toys. But if you stop to consider how each new wave of applications powered by these devices impacts the underlying SoC designs, you quickly realize that the memory and storage subsystem is now central to SoC Realization. Poor memory and storage design will impact everything from the user experience to the applications that are possible…

Verifiers rejoice: today is the 1st anniversary of the launch of this blog!!!  To commemorate the occasion, allow us to highlight the top 5 posts (out of 25 total!) from the past year.  Without further adieu, in ascending order of web hits and comments received ...

#5 - "Everything Assertion Based" -- Assertion-Based Verification (ABV) Comes of Age for Complete Block-Level Verification
This post dares to claim that…

The UVM 1.0 release was the big story of DVCon 2011, as it's the first verification methodology officially supported by all three of the "Big 3" simulation vendors.  However, the very nature of the standard -- an open source library governed by a community similar in character to Linux itself -- also enables a whole host of vendors from pure-play IP companies to providers of best-of-breed productivity tools…

As regular readers know from previous posts, I have a lot of background in assertion-based verification (ABV) and how assertions are used in simulation and formal analysis. There has been a lot of growth in the use of both assertions and formal since I was first involved in these technologies in 1999, but it would be disingenuous of me to suggest that ABV is as mainstream as I hoped it would be by now. Assertion…

The ADW16.3 Allegro Design Workbench has a new Configuration Manager that simplifies installation and configuration of the ADW server and clients.

You can now report on the status of the server and it provides status on the following:

• Server version
• Memory allocation
• Log file location
• Database information

It allows you to easily create client installs for ADW and can be invoked as a batch script:

 

Read on for more details ……

While there was a lot (justifiable) buzz around the UVM 1.0 release, formal and assertion-based verification (ABV) technologies and methodologies also had a great showing at DVCon 2011.  Beyond the many papers and posters on this topic, further evidence of formal verification growth is the emergence of service providers that are exclusively focused on this category.  Specifically, Oski Technology -- "the world's first and…

The current Allegro PCB Power Integrity (PI) tool is fast, but not accurate enough in the high frequency band due to the effect of discontinuities. This feature uses a discontinuity model in the PI analysis. With discontinuity model integration, PI analysis is more accurate and allows you to control the target impedance more efficiently.

A plane pair can be simulated by an equivalent circuit of a grid of transmission…

The nport component located in analogLib can be used in circuits for Spectre and SpectreRF simulations. It is a scattering parameter (S-parameter) based distributed multi-port element. The nport truly is a "black box"… It can be used to model dramatically...

The SPB16.3 Allegro PCB Editor has a new 3D Viewer!

Viewing a 3D rendering of the Allegro design is now available with the 3d_viewer (View — 3D View) command. The 3D Viewer is invoked in a separate window which includes viewing filters; choice of solid, wire frame or transparent graphics; and controls to pan, zoom, and spin the display.

 

The 3D viewer also operates in pre-selection mode. This mode makes it possible…

At DVCon 2011 I had the opportunity to catch-up with NextOp's CEO Yunshan Zhu, where in this video he shares some anecdotes about the BugScope's performance in real world customer environments (including accelerating assertions in Palladium with -0- (zero, zip, zilch, nada) hardware overhead!), and how their technical success is to translating to the bottom-line.

If the video fails to play, click here.

Note: we…

We interrupt our technically oriented blogging to shamelessly promote a free webinar we are giving on SoC Connectivity checking this Thursday March 24 at 10am-11am Pacific time.  At first glance, this topic doesn't seem like such a big deal - after all, checking IP-to-IP and point-to-multi-point connections is usually done by a well-organized Co-Op student, or obviated by using some sort of "correct by construction" methodology…

A Chinese design engineer told me that his manager once told him:  "You do not have to have creativity but you must know how to imitate!" This is kind of a reflection of the rapid technology growth in China for the past decade, where many of the technology advancements came from learning the latest and best technologies from the West.

When we planned for the worldwide Cadence EDA360 Tech-On-Tour mixed-signal…

As more and more custom/analog designs migrate to advanced process nodes (<65nm), design teams are being confronted with an ever-increasing need to better manage the impact of parasitics throughout the entire custom/analog design flow. In addition, more and more layout design teams are finding themselves drawn into the front-end design team's simulation flow and their path to parasitic closure.

But why is a new…

Object Linking and Embedding (OLE) support in SPB16.3 Allegro Design Entry CIS (or Capture) allows you to embed or link an object on your schematic page. The object types that you are allowed to embed or link are defined by the applications and files available on your computer. This feature allows you to annotate your schematic pages with any external data (information) that you need to enhance the usability and readability…

Smaller process technologies are enticing chip makers with bigger rewards from their end products. The shorter gate lengths at 28nm promise faster transistor speeds and less leakage power, and can double the amount of the logic that can be put into the same die area. Most importantly, however, more die on a wafer means lower per unit cost. 

Meanwhile, design complexity is compounded as chip content grows significantly…

Software, like fine red wine, can get better with age as well -- but it requires constant advancements to remain a vibrant contributor.  Such is the case with the Virtuoso IC6.1.5 custom/analog technology release, which delivers on the promise of Silicon Realization with capabilities that maintain design intent throughout the custom/analog flow, simplify the abstraction of analog information to provide high-performance verification…

• How do I simulate a transmit mixer?

• How do I look at both upper and lower sidebands?  

• How do I set up my simulation for PAC and Pnoise?

• When I plot my data, how do the indexes correspond...

The ADW16.3 Allegro Design Workbench has a desktop cockpit that allows engineers to view their internal design processes and the applications applicable to each of the steps in their flow. The Workbench guides the engineer through the flow and provides a consistent approach to otherwise disparate processes across the entire design team. The Allegro Design Workbench (ADW) is fully configurable so that it can be modified…

At DVCon 2011, a paper presented by Freescale and Cadence described a truly novel application of formal technology for something completely different than assertion-based verification (ABV).  Specifically, the authors used formal engines to optimize the selection of complex (read, "higher in area and power consumption") vs. simple (read, "lower power, lower area") power control flip-flops. In this short video, one of the…