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In case you missed any of the 5 free webinars Team Verify presented in 2011, you're in luck: all of them have been recorded and posted for you to review at your leisure. Take your pick from the following - or pop a bucket of popcorn and a family sized bag of chips and watch them all at once!

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How to Completely Eliminate SoC Connectivity Bugs - Really!

http://www.cadence.com/cadence/events/Pages/event.aspx?eventid…

My last "real-world assertions" blog post seems to have tickled a bunch of people with my story about the racy narration at the historic Red Fort in Delhi. I've heard from several folks who have also seen the show and had a similar reaction. Just out of curiosity, I did a Web search and found a half-dozen or so other blogs and travelogues with comments similar to mine. Concluding my series, and in the spirit…

The introduction of Apps in the new Cadence OrCAD Capture Marketplace in the 16.5 release brings a new level of feature customization to the designer in a proven, successful, delivery model. But what does this “design by plug-in” or “app-based” model really mean for users?

Apps, short for applications, are additional software designed to perform specific tasks. There are a vast array of design flows…

Continuing the series that introduces you to the people that create the tools you use every day, in this video R&D lead for expert-level use cases in Incisive Formal Verifier (a/k/a "IFV") Pradeep Goyal talks about the common use cases for "pure" formal users. He also notes how expert-level formal techniques might evolve over the next 5 years -- both alone, and in combination with simulation technologies…

Allow me to interrupt the excellent "Meet R&D" series to share a small holiday present.   On the Functional Verification Shared Code Forum I've just posted a ZIP file with Sudoku solver code for Incisive Enterprise Verifier (IEV). The file is at /forums/T/21110.aspx

The Details:
First, we map a standard 9x9 Sudoku puzzle into a 9x9 Verilog number array with unknown (X) locations, and then apply 3 sets of…

Although many automatic layout generation tools are available to automate design creation, the layout modification/correction step (fixing design rule violations) is not automated very well.  Consequently, design modification including error correction typically needs to be done manually. A good solution to automate the layout modification/correction step can be provided by a layout optimization tool that optimizes the…

The acid test of any conference is how long the information and lessons learned linger in your mind after the keynotes, panels, and demos wrap up.  Like last year, the 2011 edition of ARM Techcon is passing the test of time.  Below are some of the highlights that have stuck with me and/or have been prompted by follow-on news since the event.

This year's ARM Techcon highlighted advances on many fronts -
semiconductor…

Your favorite verification engineer has been good all year.  Thousands of tests run. Nights and weekends of debug.  So how do reward her? Why, with UVM Training, of course!

Cadence experts have trained hundreds of engineers on OVM and UVM.  These trainers have deep knowledge in both the methodology and the Incisive simulators that run it.  They track the latest activities in the Accellera Systems Initiative standards committee…

The 16.5 AMS library has a range of new models that can be used in diverse applications such as power supply, regulation and monitoring, and signal isolation. The new models include the following:

•    MOSFET Drivers
•    Alkaline Battery
•    Supervisory IC
•    Optocouplers

In addition, PWM and vendor models have been integrated with PSpice.

Read on for more details …

MOSFET Drivers
Two new MOSFET drivers, ISL6614…

On day-three of the Cadence Signal and Power Integrity Three Day Event, the audience was served up a dose of Robert Hanson expertise on managing power delivery networks.  Robert covered topics such as developing a bypass system, RLC of a bypass capacitor, power delivery, and capacitor parameters.  Robert interacted with the attendees in such a way that both those with a background and those without a background in the topic…

On day-two of the Cadence Signal and Power Integrity Three Day Event, it was standing room only as 100+ attendees listened in as Robert Hanson explained high speed interface design challenges associated with DDR3 and PCI Express 3.0.  Robert took the mystery out of designing for timing compliance as well as how to meet bit error rate specifications on multi-gigabit interfaces.

Robert's material on multi-gigabit interfaces…

amsDmv (Analog Mixed Signal Design and Model Validation) is an application integrated in the Cadence Virtuoso GUI flow and it can also be invoked from command line with some feature limitations. amsDmv can be used to compare the simulation restults and design interface (pins) from the DUT with those from the reference design. Therefore users can use amsDmv to validate behavioral models with original transistor level models…

On day-one of the Cadence PCB Signal and Power Integrity Three-Day Event, over 100 professionals gathered in the auditorium at Cadence headquarters eager to learn from Robert Hanson’s presentation on Signal Integrity basics.  The presentation started with the Fundamentals of Signal Integrity and moved on to transmission lines, crosstalk, termination strategies, and concluded with the effects of vias on high speed…

Continuing the series of introducing you to the people that create the tools you use every day, in this video the R&D Architect of Incisive Enterprise Verifier (a/k/a "IEV") Vinaya Singh talks about the advantages of combining formal and simulation technologies, the most common misconceptions people have about mixing the two, and where this technology might go in 5 years time (preview: beyond RTL verification…

A schematic page often contains a large number of different types of objects like parts, pins, buses, wires. Designers often need to perform operations like adding new objects, changing object properties, moving, constructing and deleting objects. All these operations require extensive user interaction with the Capture interface.

With the increasing complexity of designs, the number of objects on a page and pages in a…

OVM users have something new to give thanks for this holiday season -- an update to the OVM Register Package (new link!!). This package is used by novice and advanced users and embodies years of experience gathered through hundreds of SystemVerilog projects.

The Cadence genIES team has been remiss since the demise of the OVM World, which left the OVM community to use OVM_RGM 2.5.  We did try to post to UVM World, but that…

Cadence is pleased to be honored by the OpenText Global Partners Program as their 2011 Connectivity Partner of the Year.  The award is a reflection of the close working relationship that we have had with OpenText over the past several years, providing our mutual customers with the best experiences when using Cadence Virtuoso tool suite with OpenText's ExceedOn Demand product line, which provides remote access to Virtuoso…

Inspired by the positive response to my interview of Formal R&D Distinguished Engineer Alok Jain, while I was in India for CDNLive! I jumped at the opportunity to introduce to this community to more leaders in our R&D organization -- people that directly drive the development of the tools you use every day.  Hence, in this video Incisive Formal R&D team leader Deepak Pant talks about how formal has gone well beyond…