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At DVCon 2011, a paper presented by Freescale and Cadence described a truly novel application of formal technology for something completely different than assertion-based verification (ABV).  Specifically, the authors used formal engines to optimize the selection of complex (read, "higher in area and power consumption") vs. simple (read, "lower power, lower area") power control flip-flops. In this short video, one of the…

Clearly UVM 1.0 was the main story at DVCon last week, but there was other big news in verification IP that bears repeating.  Specifically, last week Cadence announced a new Verification IP ("VIP") Catalog -- a complete combination of standards-based Cadence and ex-Denali verification IP, supporting 3rd party simulators and hardware-assisted verification.  In this video taken on the DVCon 2011 expo floor, my colleague…

The DVCon 2011 conference was held this week and the Accellera Universal Verification Methodology (UVM) 1.0 release is breaking records in term of interest and attendance.  UVM 1.0 is a big deal(!) The core functionality is solid and ready for deployment.  Accellera held a full day tutorial on UVM 1.0 on Monday.  And during a panel discussion on Tuesday afternoon, AMD and Intel announced that they are in the process…

As I write this, I've just returned from the most important conference and tradeshow of the year for functional verification: DVCon in San Jose. The "DV" officially stands for "Design and Verification" but most people think that it means "Design Verification" since the focus has been almost entirely on functional verification in recent years. This week's conference was dominated by two big themes…

I wrote about the new Cadence Online Support features in one of my blog posts last year.

One of our Silicon Package Board (SPB) Customer Support AEs suggested that I include the Cadence Online Support Product Page URL whenever I write about a specific product’s feature. I will be doing that -- a great idea! While my first post talked about some highlights of the product pages, I thought I’d take this week to review the…

Are you looking for new approaches to improve your verification productivity by 40 - 60%? Look no further... read the technical application note by Corey Goss on how to Improve Verification Productivity through Adopting Dynamic Load and Reseed Methodology. Attached is a link to the application note that provides the technical details and the benefits of using this new advanced functionality. 

Specman Advanced Option Appnote…

The other day a designer E-mailed me: How can we rename a net in Encounter?

I followed up to clarify whether the designer wanted to change the net associated with routed wire segments, or wanted to rename a signal net. He clarified that he wanted to change a logical signal net's name.

Changing the net name associated with a routed wire segments is described in this solution:

editSelect -nets VDD1
editSelectVia -nets…

Next week my colleagues and I will be at DVCon 2011 in force, ready to regale you with technical papers, panels, and techtorials covering the full range of functional, assertion-based, mixed-signal, and transaction-level verification topics.  If you are within a tank of gas or a Southwest flight of San Jose, going to DVCon is a no brainer.  I guarantee that you WILL learn something -- whether it's from the aforementioned…

Signals are subject to degradation when they are transmitted through a channel. High speed signals are especially susceptible to degradation as loss and distortions tend to be frequency dependent. Channel characterization and multi-million bit simulations can be used to investigate these issues in greater detail. However, such investigations are time consuming for PCBs with several high speed nets.

Signal Quality Screening…

As I hope you have all seen by now, Accellera has announced the official production release of the Universal Verification Methodology (UVM) 1.0 standard. My colleagues Richard Goering,  Stan Krolikoski and Adam Sherer have already blogged about the release and its contents so I'll refer you to their posts rather than cover the same ground here. What I really want to do is to congratulate the Accellera VIP Technical…

For just over two years I have had the honor of playing a role in a dramatic example of EDA360 in action --  the creation of the Accellera UVM standard 1.0. I could not be more proud!

Many will measure UVM 1.0 in terms of features, but it is much more than that.  It represents a different way of conducting the business of verification in today's electronics industry.  Our business is changing -- the cost of finer process…

I'd like to continue my blog series discussing corner-case conditions of various kinds that I have encountered in my engineering career. So far they've all had happy endings. I discussed a software bug that was only in a prototype, not an actual product, so no real damage was done. I described a subtractor bug and a class of interface bugs in hardware, all of which were caught in verification prior to chip fabrication…

The great architect Frank Lloyd Wright once said "you can fix it on the drafting board with an eraser, or on the construction site with a sledge hammer." The semiconductor design industry is a perfect example where finding issues later in the flow can be extremely expensive. Chips that fail in high-volume consumer products can cost companies hundreds of millions or even a billion dollars, and there is huge benefit…

This is a guest post from Jason Gentry at Avago. I hope you enjoy this useful piece he's contributed on using the Encounter Digital Implementation System's dbShape command that debuted in 10.1.

I figured it was time for another guest blog, especially since I've been able to play with one of the new-to-EDI10.1 commands called "dbShape."  During CDNLive! 2008, one of the topics I talked about was…

Just a quick post this week on a new Allegro PCB Router feature in the SPB16.3 release. A small feature, but very useful!

Highlight/Unhighlight bbvias

The following command is accessible in SPB16.3 SPECCTRA to highlight/unhighlight selected kinds of blind and buried vias (bbvias):

        highlight <object_type> [<start_layer> [<finish_layer>]] on|off

object_type::= bbvias | blind_vias | buried_vias

start_layer…

In the last post of this series, we will address the last but not least of three key questions to be answered with coverage in formal verification:

• How good are my formal constraints? (Addressed in Part 1)
• How good is my verification proof? (Addressed in Part 2 and "2A")
• And today's question, "How can I feel confident my verification is complete…

The design and verification methodology for analog circuits has not changed much over the past decade. But the complexity of analog designs has grown exponentially. Analog parts are not just on the peripherals of SoCs any more. It is very common to have complex analog IP in applications such as communications, transportation and bio-medical devices. So it is not enough to just verify analog designs in isolation.

There…