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Just a quick post this week on a new Allegro PCB Router feature in the SPB16.3 release. A small feature, but very useful!

Highlight/Unhighlight bbvias

The following command is accessible in SPB16.3 SPECCTRA to highlight/unhighlight selected kinds of blind and buried vias (bbvias):

        highlight <object_type> [<start_layer> [<finish_layer>]] on|off

object_type::= bbvias | blind_vias | buried_vias

start_layer…

In the last post of this series, we will address the last but not least of three key questions to be answered with coverage in formal verification:

• How good are my formal constraints? (Addressed in Part 1)
• How good is my verification proof? (Addressed in Part 2 and "2A")
• And today's question, "How can I feel confident my verification is complete…

The design and verification methodology for analog circuits has not changed much over the past decade. But the complexity of analog designs has grown exponentially. Analog parts are not just on the peripherals of SoCs any more. It is very common to have complex analog IP in applications such as communications, transportation and bio-medical devices. So it is not enough to just verify analog designs in isolation.

There…

This week, I’m tossing together a mix of a few new SPB16.3 Allegro PCB Editor features.

Show Measure any Layer

In the SPB16.3 release, the show measure (Display — Measure) command now measures the separation between any two objects regardless of the layer. For padstacks, the active layer as shown in the Options panel is used to determine the layer of interest. If the padstack doesn't exist on that layer then…

Mobile, automotive, consumer and medical applications require the productive realization of large and complex mixed-signal systems in silicon, and they must be on time and within budget constraints. Process capabilities make it possible to implement analog and RF circuits in CMOS technology at advanced nodes, and to integrate analog and digital functionality at the system-on-chip (SoC) level. However, mixed-signal SoC…

Today at DesignCon, drop by the Cadence booth to see TeamAllegro continue the demonstration of our new power delivery network (PDN) analysis technology for PCB design and analysis.   See how during the pre-route phase of PCB design, plane shapes can be planned and optimized along with the PCB stackup.  Analysis will show where resonant frequencies are likely to exist and adjustments can be made to planes, the stackup, and…

The Allegro Design Entry CIS (Capture - Allegro flow) now includes an object locking feature. This feature allows you to temporarily lock and object on your schematic or board while you are cross-probing. This will help to avoid shifting (with the potential of breaking connectivity) a component on the schematic or board during the cross-probe operation.

When you cross probe between Capture and Allegro PCB Editor, you…

Today at DesignCon, drop by the Cadence booth to see TeamAllegro demonstrate the new power delivery network (PDN) analysis technology for PCB design and analysis.  This is important because higher speed technologies such as DDR3 require lower voltages.  Lower voltages provide less margin for IR drop caused by power and ground planes that are carved up to meet design miniaturization requirements. 

However, locating an IR…

The Cadence booth at DesignCon 2011 will provide visitors with a demonstration of new technology that has been developed for analysis of the power delivery network (PDN) of a printed circuit board (PCB).  This new technology features enhanced static IR drop analysis, and is the foundation of a complete re-design of the power integrity tool that Allegro PCB users have worked with for over ten years.

The new PDN analysis…

My last few blog posts have included three corner-case conditions that led to bugs, one in software, one in hardware, and one in real life. One of the reasons that corner-case conditions are missed is that some engineers don't spend enough time really thinking about their design and documenting its intended functionality. Writing specifications that are orthogonal to the specific hardware or software implementation…

Recall that three main questions need to be answered to attain coverage in formal verification:

• Part 1 of this series addressed, "How good are my formal constraints?"
• In Part 2 we showed debugging of over-constraining with help of examples, addressing the question, "How good is my verification proof?"
• In a subsequent post we will address the third key question "How can I feel confident my verification…

Here are just some of the new capabilities available in the ADW16.3 Allegro Design Workbench (ADW) Library Revision Manager (LRM) and Component Browser (CB)

• LRM:
  • Detects deleted parts and models
• Component Browser:
  • Identifies parts removed
  • Identifies pre-released parts
  • Identifies parts with lifecycle  warnings
• Design_reports
  • Pre-release models and parts
  • Deleted models and parts

Some features of fixing deleted parts / models:

• Navigate…

1.1: (defun walkCvHier (cv consume)
1.2:   (foreach inst cv~>instances
1.3:     (walkCvHier inst~>master consume))
1.4:   (consume cv))

Just to reiterate: this…

There is no doubt in my mind that assertions will play a significant role in analog verification, be it verifying individual analog blocks or a complete mixed-signal SoC in the near future. So yes, it is for real and it is here to stay. I hope to convince you in this blog that you should take a closer look at adopting assertion based verification (ABV) for your next mixed-signal design. I have worked on assertions extensively…

Kicking off 2011, my colleague Alok Jain -- a Distinguished Engineer at Cadence who directs the company's R&D efforts in formal verification -- spoke with Industry Insights columnist Richard Goering.  In a wide ranging interview they discussed formal verification usage trends, benefits, roadblocks, appropriate coverage metrics, and the growing alignment of simulation and formal to speed Silicon Realization.

In this…

As noted in the prior installment of this series, there are three main questions to be answered with coverage in formal verification:

• How good are my formal constraints?
• How good is my verification proof?
• How can I feel confident my verification is complete?

In Part 1 we began to address the first question, and in this post we will continue to discuss it in the context of debugging over-constrained verification environments…

The SPB16.3 release of Design Entry HDL (DEHDL) provides an easier method for setting up the PCB SI model library path, and brings more consistency to the Front-to-Back (F2B) and Back-to-Front (B2F) flows.

Signal Integrity (SI) models are essential for running an SI simulation. PCB SI is an integrated solution with DEHDL and Allegro PCB Editor. When a design is moved from one engineer’s system to another engineer’s system…

A recent customer blog interview with Geoffrey Faurie from ST Microelectronics and Richard Goering from Cadence was posted on Cadence.com with the title: "Is e or SystemVerilog Best for Constrained-Random Verification?" This blog post has received much positive feedback from other Specman/e and SystemVerilog users. Whether you are a Specman/e and/or SystemVerilog user, this blog provides a good balance of the…

Advanced verification customers are seeing their verification environments getting more and more complex requiring millions of lines of code spread across hundreds, even thousands of files that are re-used from Block --> SoC --> System level. Today's design under test (DUT) can be extremely complex and, as a result, verifying every feature, in every mode of operation, under all conditions is extremely difficult to achieve…