Community

The Allegro Design Workbench (ADW) Configuration Manager application is designed for an administrator to manage the ADW environment including:

• Server / Client Installation Configuration
• Company and Site configuration
• Server status
• Metrics Dashboard

It provides a single location where the ECAD environment can be managed and reported on. In ADW 16.5 the focus has been on:

• Site Management
• Metrics Dashboard

Read on for more details…

The first "Club Formal" event in China was held in Shanghai on Oct. 21 2011, and as you can see in the image gallery below 24 customers from different 6 companies came together to share their general experiences and detailed case studies on formal and assertion-based verification (ABV).  We also took the opportunity to announce and demonstrate some new technologies, share our product roadmap, and learn new requirements…

• In Part 1, we saw the rules of sudoku and a brief introduction to the SKILL++ Object System.
• In Part 2, we started solving the problem top-down by implementing the top level function SkuSolve and agreeing to fill in all the missing pieces incrementally until the program was complete. We also saw how to use hierarchical…

Recently I had the honor of presenting the functional verification roadmap at CDNLive! India in Bangalore.  With the high quality of content and networking, it was easy to see why attendance has increased year-over-year; and why CDNLive India has become the premier conference on the region's engineering community calendar.  The following video montage should give you a flavor of the event (if video does not appear,…

There are several enhancements in the 16.5 System Connectivity Manager (SCM)  / Allegro System Architect (ASA) product that I’ve compiled below that I'm sharing in a brief post this week. Please take advantage of these new 16.5 capabilities.

Refresh Option in File Viewer
We now have the option to 'Refresh' the File Viewer. Right click in File Viewer Window and select – Refresh:

 

Copy Project
This option…

Please join Team Verify and other D&V engineers for one or both of the following free events over the next 2 weeks:

* This coming Tuesday November 8 starting at 11:30am on our San Jose campus, we are holding the next installment of "Club Formal."  The main topics for this event will be abstraction and coverage unreachability methodologies.  Here are more specifics: http://www.cadence.com/cadence/events/Pages…

The Call for Papers for CDNLive! Silicon Valley 2012 is open now through Friday November 11th, 2012. CDNLive! is the Cadence users group conference. It provides an opportunity to present and listen to presentations from folks who use Cadence software to get their jobs done. Next year's conference is being held March 13-14 2012 at the Doubletree San Jose.

I've attended a number of these events in the past, both as a…

This is the second installment in an ongoing series of blog posts that includes an email conversation between Fred and Harry, two fictional mixed-signal engineers, about analog behiavoral modeling. You can read the first installment by clicking here. (NOTE: This blog post was written by Walter Hartong and uploaded by Paul Foster).

Hi Harry,

As I said, this was really the fun stuff. We are coming into the region of 1000x…

I am often asked for guidelines on maximizing speed vs. accuracy for SpectreRF harmonic balance simulations. 

Today, I'll discuss part 2 of the 3 part series consisting of:

• Which Engine:  Spectre or APS?
• Oversample vs Number of Harmonics
• Harmonic Tr...

Due to architectural changes in SPB16.5 Design Entry HDL (DEHDL), we no longer require various modes of operation -- such as Hierarchy mode, Expanded mode and Occurrence Edit mode. There will be no need to change modes while working on the schematic since the explicit need for design net listing and design expansion is removed. This is a HUGE simplification from prior releases!

Read on for more details …

Designs…

Introduction

This is the first of a series of blogs where we will add pieces to the story over time. This is an email conversation between Fred and Harry, two fictional mixed-signal designers, where Fred is adopting various modeling techniques to realize faster simulations while maintaining acceptable levels of accuracy. (NOTE: This blog post was written by Walter Hartong and uploaded by Paul Foster).

How Fred came to mixed…

[Author unknown]

Last week (October 23rd, 2011 or 24th depending on which source you read) we lost Dr. John McCarthy, one of the great contributors to the field of computer science. I'd like to send my condolences and best wishes to friends and family he left behind.

John McCarthy was the 1971 recipient…

On October 19, 2011 in Bangalore, India more than 800 engineers across all domains came together for CDNLive India 2011.  Among the attendees were over 300 design and verification professionals who focused on the functional and system verification tracks.  In this post I'll pull together some highlights from the customer presentations, with particular emphasis on the papers about formal, formal combined with simulation…

There are currently multiple options for model editing in the Allegro PCB SI environment. These include the legacy dialogs within the PCB SI and SigXplorer environments. Although these dialogs provide graphical editing, they are cascaded through many levels and default to text editing for certain model types. The goal is to provide a single environment for model editing and validation for all applications, and to replace…

All pun-tastic references aside, connecting SystemVerilog and SystemC is becoming a commonplace request.  In most cases, the request is to do this using UVM as the testbench methodology. One of our resident technical experts, Phu Huynh, will lead a webinar on this subject on October 20.

Cadence pioneered efforts to connect a major methodology across multiple languages in 2009 with the release of OVM multi-language support…

In the distributed co-design environment in the SPB16.5 Allegro Package Designer release, a die abstract file is used to convey die information between IC and package layout tools. For ECO purposes, it is imperative to know the changes that are incorporated inside an abstract file before incorporating them in the database. The Component Compare feature in SiP allows you to view differences between die layout information…

(defun SkuSolve (partial_solution)
  (let ((sudoku (SkuInitialize (SkuNew) partial_solution)))
    (printf "starting with: \n%s\n"
            (SkuPrint sudoku))
    (printf "\nfound solution:\n%s\n"
            (SkuPrint (SkuFindSolution sudoku…

Well, here I am embarking on my fifth post in which I point out illogical situations I'm come across in my daily life and suggest that the real world is missing some useful assertions. What started out as a fun way to fill a blog post has turned into a series that has received a lot of positive feedback and, as I mentioned in my most recent post, plenty of page views. I'm beginning to wonder if I'm beating this…

At the Electrical Performance of Electronic Packaging and Systems conference (EPEPS 2011) in San Jose, Calif. Oct. 23-26, Cadence will demonstrate our latest technology developed for PCB multi-gigabit design and analysis. Join the buzz at Table 8 while the exhibits are open on Monday and Tuesday (10/24-10/25), as our product experts will be available to discuss and demonstrate 3D Full-Wave Analysis Technology integrated…