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Advanced verification customers are seeing their verification environments getting more and more complex requiring millions of lines of code spread across hundreds, even thousands of files that are re-used from Block --> SoC --> System level. Today's design under test (DUT) can be extremely complex and, as a result, verifying every feature, in every mode of operation, under all conditions is extremely difficult to achieve…

So I know you tell your kids this, you tell your spouse this, you heard it from your parents and they from theirs, yet somehow when it comes down to it -- it always seems easier to "do" than to "plan."  Even redo seems easier than to actually spend the time to write out a meaningful plan and then execute to it.  So why does the recent Cadence verification news revolve around the verification plan…

As with every new release, a primary focus for the Allegro Package Designer (APD) PCB IC Packaging tools is the wire bonding capabilities. These are some of the most frequently used, complex, and crucial commands in the tool. As the majority of packages today are still based on wire bond technology, and this is getting only more important with new technologies like stacked dies and silicon interposers, an intense focus…

Simulation failures are seen quite often in design verification.   Fortunately, with the new Cadence Silicon Realization approach, you'll have the tools necessary to quickly get back to simulating.  The complete solution for determining what is causing your simulation to fail is SimVision, part of the Cadence Incisive Enterprise Simulator. 

You probably saw the recent press announcement, "Cadence Boosts Verification…

We interrupt R&D's Vinaya Singh's excellent series on "The Role of Coverage in Formal Verification" to reference a related post from Richard Goering on "Extending Metric-Driven Verification (MDV) to Formal Analysis - What, Why, and How".  Specifically, Richard's article shows how coverage from formal analysis (described by Vinaya) is tied into what has been a traditionally dynamic simulation…

Last May, I posed a question about what EDA360 means for verification engineers. Yesterday we made an announcement about verification for Silicon Realization that is a big deal. We are delivering a lot of new technology with immediate and high value to verification engineers everywhere. My colleagues will be blogging on many of the details, so let me focus on what I think are the three biggest announced verification…

Facing a verification overrun, you poached resources, clocked overtime, and kept the slip to a few weeks.  Momentarily proud of your diving catch, your GM just told you to get out on the road to sell an additional 400,000 units or your program will be canceled. As you examine every customer looking for the elasticity that will keep you profitable, you plan to find a new approach to Silicon Realization.

This is the reality…

Even before the snap you need to check the environment statically to eliminate bugs. The 700+ rules in…

Previously I wrote about the basics of feedthrough insertion in Encounter.  Today I'd like to push into a tiny but powerful example of how Encounter's feedthrough insertion solution can derive solutions that enable rapid top-level design closure.

Feedthrough insertion in Encounter has two modes of operation: Placement-based -or- route-based.  The advantage of route-based is its awareness of congested vs. sparse areas…

Happy New Year!

Electromagnetic Solution 2D (EMS2D) is designed for accurate transmission line parameter extraction over a full frequency range from DC up to the frequency of interest. However, this accuracy depends on an accurate and complete physical model provided to the solver by users. For example, the parameter for conductor surface roughness is missing from the input parameter list to the solver.

In multiple GB…

The way SKILL++ deals with functions is a bit different than the way traditional SKILL deals with them. In this posting I'd like to show how to implement a design hierarchy traversal engine in SKILL++ and use it as an introduction to SKILL++.

What is SKILL++?

SKILL++ is a subset of the SKILL language, not a separate language as one might suppose. The term SKILL++ refers to a small but powerful set of extensions…

In a recent blog post, I talked about learning a public lesson on the importance of software verification while an intern at Digital Equipment Corporation (DEC). Since I spent most of my early career as a logic designer, not a programmer, I figure that an example of a corner-case condition from that part of my life would also be nice to share. This story will doubtless remind you of a well-known "divide …

As outlined in a prior post, new advances in formal and multi-engine technology (like Incisive Enterprise Verifier  or "IEV") enables users to do complete verification of design IP using only assertions (i.e. no testbench required!) -- especially for blocks of around 1 million flops or less.  Given this premise, it's natural to ask: "OK, but how does formal and multi-engine assertion-based verification…

Since the initial release of Advanced Constraints, one of limitations was that formulas had to be recalculated manually. This recalculation could be done on an individual basis or for the entire design with the Calculate All command. The Online Formula Calculation feature addresses these limitations by tracking the dependencies that formulas have on design objects and updating the formula automatically.

The SPB16.3 release…

If you were not able to attend this recent live webinar, or were able to and would like to share the content of this webinar with colleagues, you can find an on-demand recording by clicking and registering here:

Managing parasitics in the back end

In this third of a three part webinar series on parasitic aware design, Jeremiah Cessna and Sravasti Nair present an overview and demonstration of a back end analog IC design…

Feedthrough insertion is a subtly crucial task that naturally arises in hierarchical digital design.  There are several types of approaches we can use to allow signals to traverse across a chip, but the most common and effective I've seen is where buffers are inserted in neighboring partitions.  This eliminates top-level routing and more importantly takes the top-level timing closure task and makes it part of block…

The SPB16.3 release of Allegro PCB Router is now aligned with Allegro PCB Editor's approach for verifying mechanical hole objects.

Antipad as Route Keepout (or ARKs)

The Antipad as Route keepout option can be enabled in pad_designer:

 

The ARK on option is translated to a SPECCTRA dsn file as shown in example below:

  (padstack PAD125
   (plating nonplated)
   (ark on)
   (type thrupad)

The new behavior of Allegro PCB Router with…

If you were not able to attend this recent live webinar, or were able to and would like to share the content of this webinar with colleagues, you can find an on-demand recording by clicking and registering here:

Managing parasitics in front end

In this second of a three part webinar series on parasitic aware design, Nigel Bleasdale and Stacy Whiteman present an overview and demonstration of a front end analog IC design…

As 2010 ends and 2011 begins, the most important thing that came out of the Universal Verification Methodology (UVM) was the UVM Reference Flow.  We are thrilled with the results coming from this community contribution. With over 1,000 downloads already, it is clear that UVM has moved into the mainstream -- not a bad year at all.  Not only will the UVM libraries officially be released from Accellera after a significant amount…

If you were not able to attend this recent live webinar, or were able to and would like to share the content of this webinar with colleagues, you can find an on-demand recording by clicking and registering here:

Parasitic Aware Design - A Complete Analog Design Flow

In this first of a three part webinar series on parasitic aware design, John Stabenow presents a high level overview of an end-to-end analog IC design flow…