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Digital Design: Five-Minute Tutorial: ecoAddRepeater

Kari

In today's tutorial, we're going to talk about the Encounter Digital Implementation (EDI) system command ecoAddRepeater. You may have come across this command and even used it before, or perhaps you used the GUI (Optimize->Interactive ECO...) to add buffers or inverters, and didn't know that this was the command doing the work. Either way, let's review some reasons we'd want to use such a command.…
- 19 Oct 2010
SoC and IP: Angelbird Ltd. Introduces “Wings,” a low-cost PCIe SSD for PCs. $239 for 16 Gbytes

archive

Stop me if you’ve heard this one. The fastest way to get high performance from an SSD is to bypass the disk interface and plug the SSD directly into the PC’s PCIe port. Vendors of high-performance (read “expensive”) SSDs do just that. So just where does startup (or is that “upsart”) Angelbird Ltd. get the moxie to announce a PCIe-based SSD card that sells for $239? The card is called “Wings” and is said to boot on PCs…
- 19 Oct 2010
SoC and IP: Hitachi-LG Data Storage fixes optical drive with SSD assist to use one SATA port

archive

Hitachi-LG Data Storage has updated the hybrid optical/SSD drive it announced earlier this year (How does a hybrid SSD/optical drive make sense?) by integrating the SSD with the optical drive controller and making both the optical and solid-state drives accessible through one 6Gbps SATA III port. The first-generation drive introduced earlier this year at the Computex electronics show in Taipei was essentially an SSD tacked…
- 18 Oct 2010
SoC and IP: Made in South Korea: Graphene memristor memory cells on a flexible plastic substrate

archive

IEEE Spectrum has just reported on the successful fabrication of graphene-based memory cells on a flexible plastic substrate by Sung-Yool Choi and his research team working at the Electronics and Telecommunications Research Institute in Daejeon, South Korea. The memristor memory closely resembles that of HP, using a simple crosspoint-array interconnect, with a memory cell made of graphene oxide instead of HP’s titanium…
- 14 Oct 2010
SoC and IP: Brian Fuller @EETimes: Renesas to put MRAM in 90nm microcontrollers by 2013

archive

EETimes’ Brian Fuller is blogging live from the Renesas DevCon down in southern California and he reports this morning that Renesas has announced plans to incorporate MRAM (magnetic RAM) in its microcontrollers built using 90nm process technology, with parts to be introduced by 2013. At that geometry, Renesas expects the MRAM to support 150MHz operation. Two years later using 40nm process technology, Renesas expect to…
- 13 Oct 2010
System, PCB, & Package Design : What's Good About Allegro PCB Editor Customizable Datatips? Look to SPB16.3 and See!

Jerry GenPart

In pre-select mode Allegro displays a datatip that provides information about the element that is being hovered over. The TAB key can be used to cycle through the string of elements such as symbol, pin, and net, resulting in a new display of the datatip. In the SPB16.3 release of Allegro PCB Editor, it is now possible to customize the display through a user configuration interface. Items that can be configured include…
- 13 Oct 2010
Digital Design: 3D-IC TSV Realization: The Race Has Begun!

archive

3D IC discussions are creating quite a buzz these days. No conference is complete without a mention of 3D ICs, and there are reasons behind that. 3D ICs using through-silicon vias (TSVs) help you meet challenging performance and power targets to serve the growing demands of the networking, graphics, wireless, and computing industries. And don't forget consumer needs for ultra light and thin devices!
If you have anything…
- 12 Oct 2010
Verification: Connections Partner NextOp on Assertion Synthesis and Assertion-Based Verification (ABV) with “BugScope”

TeamVerify

As anyone working in Formal and Assertion-Based Verification (ABV) knows, the task of writing assertions can quickly overwhelm even the most patient engineer. While Team Verify has partially addressed this challenge with the "Automatic Formal Analysis" capability built into Incisive Formal and Enterprise Verifier tools, our new Cadence Connections program partner NextOp with their "BugScope" tool has taken …
- 11 Oct 2010
SoC and IP: Sandforce Enterprise-Class SSD 2500/2600 processors deliver double performance

archive

SandForce has just announced a new enterprise-class SF-2000 SSD processor family including the SF-2500 and SF-2600, which deliver approximately twice the performance of the company’s existing SF-1500 SSD processor. The new SSD processors start with SATA III 6Gbps host interfaces that have twice the maximum bandwidth of the SF-1500’s SATA II interface. Maximum sequential read/write performance is now rated at 500/500 Mbytes…
- 11 Oct 2010
Verification: Video: Interview With NextOp CEO Yunshan Zhu on Assertion-Based Verification (ABV) With “BugScope”

jvh3

What makes a startup "hot"? To be sure, trade press and blogger attention helps. But from where I sit, the truly hot companies are identified by an increasing frequency of emails from Application Engineers (AEs) and Sales people to the effect of "this new company is getting traction in my accounts - users love ‘em - are we partnering with them?"
Such has been the case with NextOp Software since…
- 10 Oct 2010
SoC and IP: Anandtech reports that Intel’s new SSDs that incorporate 25nm Flash will have 4x the lifespan rating

archive

This blog previously reported that Intel will be rolling out new versions of its highly regarded X25-M SSDs. These new drives will incorporate 25nm MLC Flash devices. Now, Anandtech has reported some interesting specs. Maximum capacity is up from 160 to 600 Gbytes. Sequential read performance is unchanged at 250 Mbytes/sec but write performance will jump from 100 to 170 Mbytes/sec and the read/write IOPS ratings jump…
- 7 Oct 2010
Verification: "We Want UVM 1.0! When Do We Want it? Now!"

Adam Sherer

Short of holding signs and yelling slogans, the 12 customers I visited in the past week all declared this mantra. All are planning to move to UVM 1.0 with all of them requiring the phasing and register package capabilities, but only one also requiring TLM2 support, primarily for accessing SystemC models. The good news for them and the rest of the community is that Cadence is driving these features and more in the Accellera…
- 7 Oct 2010
Analog/Custom Design: Things You Didn't Know About Virtuoso: ADE XL--Take This Job and...Run It!

stacyw

Sometimes these articles just write themselves...
Last week, 3 different people asked me questions about the ADE XL Run Options form. Sadly, the odds that 3 people in the same week would ask a question to which I actually knew the answer are vanishingly slim, so that meant I needed to do some research. And, in the course of that research, I discovered why there were so many questions about this topic. It is quite confusing…
- 6 Oct 2010
System, PCB, & Package Design : What's Good About AMS Simulator Fonts, Models, and More? It's in SPB16.3!

Jerry GenPart

The SPB16.3 release of the Allegro AMS Simulator environment contains a few additional features (which I've not yet covered in my prior posts) that I'll wrap-up in this post.
Highlighting in circuit and out files

With the SPB16.3 release, the PSpice circuit and out file syntax are presented in easy to read colors that highlight the different groups such as text, numbers, comments, expressions, operator, and keyword…
- 6 Oct 2010
RF Engineering: Measure Twice, Cut Once for Transistor ft

Art3

Recently there was an inquiry about the methodology for performing the f_t (transition frequency) versus Ic measurement described in my Measuring Transistor f_t blog post from July 2008:
By bid75 on September 8, 2010
I am unable to understand how ft vs. Ic...
- 6 Oct 2010
Verification: Why EDA Verification is Like Pro Sports

archive

First, I would like to introduce myself. My name is Jim Kjellsen. I've recently joined the Product Management group for the verification products at Cadence. My career started as a design and verification engineer, but quickly moved over the fence to the tool provider side in EDA with Daisy Systems. From there I moved into more of a niche EDA company, Logic Modeling, which was later acquired by Synopsys. I had been…
- 4 Oct 2010
SoC and IP: Renesas introduces new 1.1Gbit low-latency DDR DRAM (LLDRAM) for networking apps

archive

Renesas has introduced a new 1.1Gbit, low-latency DDR DRAM (LLDRAM) primarily for networking applications that really need the device’s low 13.3nsec read/write latency. This part is another in the series of LLDRAMs originally developed by NEC. (Renesas and NEC announced a merger agreement last September and have now completed this action.) There are four devices in the 1.1Gbit LLDRAM family: the µPD48011318FF, the µPD48011336FF…
- 4 Oct 2010
Verification: Tech Tip: Distributing Incisive Enterprise Verifier (IEV) Engines and Assertions with LSF and Enterprise Manager

TeamVerify

A common problem when distributing engines and assertions in Incisive Enterprise Verifier (IEV) and Incisive Enterprise Manager (EMGR) at the same time using LSF with big machines is the following: if you use the "define engine auto_dist" setting, but only reserve 1 slot in LSF, then IEV will spawn off more than 16 processes within each job, overloading the machine quickly. The attention of your IT department will be…
- 1 Oct 2010
SoC and IP: OCZ invents proprietary 20Gbps link for SSDs, snubbing SAS, SATA, and PCIe

archive

Yesterday, OCZ released a curious statement saying that it was unveiling a proprietary interface it's calling the “High-Speed Data Link” (HSDL) to accelerate connection to solid-state storage. The company is apparently unsatisfied with existing interface options (SAS, SATA, PCIe) and has developed HSDL to eliminate I/O bottlenecks and enable SSD technology to operate at its full potential. One HDSL can operate at transfer…
- 30 Sep 2010
SoC and IP: Elpida announces 30nm, low-voltage, low-power, 2Gbit DDR3 SDRAM with TSV (through silicon via) 3D option

archive

The headline pretty much says it all. Memory vendor Elpida hit all the DRAM high notes in its most recent announcement of a new 30nm DDR3 SDRAM. First, Elpida says in one place in the press release that it will produce this SDRAM with a “30nm-level” process. However, most of the announcement doesn’t qualify “30nm” with “level” so this may well be a true 30nm process technology, which makes this quite advanced for an SDRAM…
- 30 Sep 2010
Verification: A Quick Check on the Status of UVM 1.0

tomacadence

Regular readers know that I've blogged a lot about the Open Verification Methodology (OVM) and the upcoming Accellera Universal Verification Methodology (UVM), whose 1.0 EA (Early Adopter) release is virtually identical to the OVM. I've been silent for a while, waiting for the Accellera VIP-TSC to complete the second phase of its work and release UVM 1.0, without that annoying and misleading "EA" label. In the meantime…
- 30 Sep 2010
SoC and IP: LSI Corp to host IC innovation conference and technology showcase in Milpitas next week

archive

On October 5 through 7, LSI Corp will be hosting a conference and technology showcase in at the beautiful Crowne Plaza Hotel in suburban Milpitas, just north of San Jose. Allow me to especially point you to two interesting panels. The first is on 3D ICs, which is a topic that just keeps getting hotter. Sure, it’s a high-volume technology, but it has fascinated vendors up and down the food chain for decades and it seems…
- 29 Sep 2010
Verification: Will Your Next System Project Succeed?

Steve Brown

Will you have the System Realization tools you need? Will you know how to apply them and not waste 6 months of your schedule? The Cadence System Realization webinars are here to help you succeed! They provide a unique view into the rapidly expanding ...
- 29 Sep 2010
System, PCB, & Package Design : What's Good About PCB SI DML Path Setting? See For Yourself in the SPB16.3 Release!

Jerry GenPart

With the SPB16.3 release of Allegro PCB SI, there’s a new methodology for Device Modeling Language (DML) path setting and searching.
In previous releases, DML and IML paths were controlled graphically with the Library Browser, as shown below:

They could also be set through the use of environment variables such as signal_devlibs:
set SIGNAL_DEVLIBS /hm/test/dml/devices.dml $ALLEGRO_INSTALL_DIR/signal/cds_models.ndx
…
- 29 Sep 2010
Digital Design: Guest Blog: Using dbTransform to Translate Geometric Coordinates in Encounter

BobD

This is a guest post from JasonG at Avago. I hope you enjoy this useful piece he's contributed on using the relative-new dbTransform Encounter command. If you'd like to write a guest post we'd love to have it. Please drop me an E-mail if you're interested in contributing: dwyer@cadence.com -Bob Dwyer
Hello fellow digital implementation Tcl developers! Bob asked if I'd be interested in contributing to a…
- 28 Sep 2010

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