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Verification: Why The UVM Is Ready For Production Use Today -- Part 3

tomacadence

This is the final installment of my blog posts based on the three common questions I heard at DAC regarding the Universal Verification Methodology (UVM). I've already answered the questions "What does the UVM mean for the future of the OVM and VMM?" and "Why is the first release of the UVM labelled as "Early Adopter (EA)?"
The third and final question that I'd like to address is "Will there…
- 7 Jul 2010
Verification: Duolog Interview At DAC 2010, And The IP Integration Aspect Of EDA360

jvh3

One virtue of events like DAC is that is provides an open forum for vendors to show how they crystallize high-level, abstract ideas to concrete, valuable products. Cadence Connections program partner Duolog made the most of this opportunity by exhibiting their "Socrates" chip integration platform for addressing the growing problem of integrating IP of all shapes, sizes, and domains -- plus maintaining all the…
- 7 Jul 2010
SoC and IP: Specialty semiconductor foundry TowerJazz licenses “Y-Flash” IP to “leading” digital foundry

archive

TowerJazz, the specialty semiconductor foundry created by the merger of Tower Semiconductor and Jazz Semiconductor in 2008, has announced that it has licensed its “Y-Flash” MTP (multiple-times programmable) CMOS memory IP to an unnamed, “leading” digital foundry. TowerJazz’s Y-Flash IP creates a Flash memory cell with standard CMOS processing. In other words, the Y-Flash memory cell has only one gate and it’s a floating…
- 6 Jul 2010
System, PCB, & Package Design : What's Good About Via DRCs In Allegro Constraint Manager? It's In SPB16.3!

Jerry GenPart

Current design technologies require extremely tight matching requirements right down to the overall net topologies to ensure that any deviations in propagation delays are minimized. As a result, design guidelines call for matching the number of vias for a group of signals. The prior releases of Constraint Manager support a "MAX_VIA_COUNT" constraint which does not meet the needs of these new design requirements. The SPB16…
- 2 Jul 2010
SoC and IP: Will Taiwan Innovation Memory Company (TIMC) become Taiwan’s NAND Flash Inc?

archive

The Taiwan Innovation Memory Company (TIMC) was originally formed as the Taiwan Memory Company (TMC) and was tasked with shoring up Taiwan’s DRAM vendors (Powerchip, ProMOS and Rexchip) and linking up with Japanese DRAM powerhouse Elpida acting as a technology partner in an attempt to put Taiwan solidly into the competitive DRAM arena. It didn’t happen. The Taiwan legislature didn’t pony up the cash to get the organization…
- 1 Jul 2010
Verification: Why The UVM Is Ready For Production Use Today - Part 2

tomacadence

In my last blog post, I talked about the three most common questions I heard at DAC from people who had some concerns about moving to the Universal Verification Methodology (UVM). I already addessed the question "What does the UVM mean for the future of the OVM and VMM?" by noting that the OVM developers are moving their focus to the UVM.
Today I'd like to address the second common question: "Why is the first…
- 1 Jul 2010
SoC and IP: DRAM vendors look to 40nm process technology to keep DRAM profits flowing next year

archive

Taiwan Economic News reports that DRAM vendors will be bringing 4x nm process technologies on line during 2010 and 2011 to keep manufacturing profits up. According to P L Pai, vice president of Nanya Technology, DRAM chip makers are presently climbing the learning curve with 40nm process technologies and he says that the lead time of 40nm immersion tools averages nine months. Consequently, he predicts that production…
- 30 Jun 2010
Verification: DAC Report: Interview With AMIQ And Update On Their “DVT” IDE

jvh3

One of the benefits of the Design Automation Conference is the opportunity to follow the growth trajectory of partner companies with each successive show. Last year our long time Verification Alliance partner AMIQ (a name familiar to many Specmaniacs) made their first appearance at DAC, and they were back in force this year with new employees and new capabilities.
In this video I interview AMIQ's CEO Cristian Amitroaie…
- 30 Jun 2010
Verification: DAC report: Video Interview With Zocalo

TeamVerify

One of the benefits of the annual Design Automation Conference is the opportunity for innovative start-ups to make their mark. This year, our partner Zocalo made several "must see lists" for their Zazz platform's ability to make life easier for IP creators and integrators with their easy to use Assertion Based Verification (ABV) tool suite.
In this brief video, Zocalo's CTO Khalil Shalish covers the highlights…
- 29 Jun 2010
Verification: Why The UVM Is Ready For Production Use Today - Part 1

tomacadence

As I mentioned in my DAC report, I spent the largest percentage of my time at the OVM-UVM booth, educating attendees on the status of the Universal Verification Methodology (UVM) and answering their questions. Many people had heard about the UVM, although some were unclear on its relation to the Open Verification Methodology (OVM). I was happy to emphasize the tight link between them.
In fact, the booth showed the two…
- 29 Jun 2010
Digital Design: DAC 2010 – A “Coming Out” Party For 3D-IC Design

RahulD

Overall, the 2010 Anaheim DAC was livelier than the years before. Customer and vendor faces were not long and serious, but more purposeful and forward-looking. The recent M&A activity also brought in some rays of sunshine. The EDA360 vision for the entire industry resonated with a wide gamut of system companies, IDM's, ASIC/IP vendors and foundries. And, the hottest topic this year definitely was 3D-IC (Stacked…
- 28 Jun 2010
SoC and IP: New Freescale ARM-M4 and ColdFire-based 32-bit microcontrollers feature on-chip nanocrystal non-volatile memories

archive

June’s Microprocessor Report carries an article written by Editor-in-Chief Jim Turley that describes two new 32-bit microcontroller families from Freescale (formerly Motorola Semiconductor)--one family dubbed Kinetis featuring an ARM Cortex-M4 processor core and the other a revamped ColdFire processor architecture dubbed ColdFire+. Both microcontroller families feature a non-volatile, “Flash-like” memory technology dubbed…
- 28 Jun 2010
SoC and IP: Intel + Best Buy + SSD = Sign of the Times

archive

Intel recently announced that Best Buy is now carrying its retail-boxed X25-M (mainstream) and X25-V (value) SSDs. The 80-Gbyte X25-M sells for $229.99 and the 40-Gbyte X25-V sells for $129.99. Neither of these drives is large enough to act as a replacement drive in most of today’s notebook or even netbook computers. However, they can serve as boot and application drives to help speed boot and load times. Nevertheless…
- 28 Jun 2010
Verification: Tech Tip On Verification Environment Re-Use

Team MDV

Verification has come a long way this past year, the highlight of which is UVM. UVM gives us verification productivity with testbench re-use because of a well defined SystemVerilog coding structure. But beyond UVM, what are the areas that are the most challenging and thus time consuming? We recently asked some of our users this question, and got some interesting answers, which are reflected in the chart below.

The interesting…
- 27 Jun 2010
Verification: DAC Perspective One Week Later

tomacadence

DAC in Anaheim last week was as busy as always, perhaps more so, and of course I arrived back in San Jose to a mountain of work set aside during the show and the run-up to it. But I have dug myself out enough to look back at DAC and make a few observations. First of all, I know that overall attendance was down but I was as busy as I've ever been there. Cadence was back at DAC in a big way, and there was a lot of activity…
- 25 Jun 2010
Verification: IntelliGen Moving Into The Spotlight With Pgen Deprecation

teamspecman
Specman's new Aspect Oriented Generation Engine, IntelliGen, has now been in service for several years and we have received much positive feedback from customers in terms of ease of use, solvability, coverage and performance. For more information on IntelliGen, check out the following links, as well as other blogs written in this forum.
Introducing Aspect Oriented Generation
Debugging with IntelliGen.
Customers employing…
- 25 Jun 2010
SoC and IP: Elpida, Powertech Technology, and UMC team up to mate SOCs and memory using 3D design and assembly, targeting 28nm node

archive

The idea of 3D wafer stacking isn’t new. I wrote an article about 3D assembly of silicon die and entire wafers using through-silicon vias (TSVs) more than 20 years ago in an EDN series titled Decade 90, but it was only an experimental technology way back then. Over the past 10 years, SIP or system-in-package assembly techniques have taken the compact mobile product world by storm, particularly in products such as cell…
- 24 Jun 2010
SoC and IP: SanDisk’s WORM (write-once, read mostly) SD card can’t be altered once written. Good for secure legal and medical applications. Good for everyday digital film?

archive

SanDisk has just unveiled a WORM (write-once, read mostly) variant of the ubiquitous SD Flash memory card that’s intended for applications where stored data must be tamper-proof and unalterable. Such situations include video, image, audio and other forms of legal evidence; business and tax records; voting records; and medical records. In all such cases, all parties must believe that the data is exactly as it should…
- 23 Jun 2010
System, PCB, & Package Design : What's Good About Vias And The Allegro Router? SPB16.3 Has A Few New Enhancements!

Jerry GenPart

A few new enhancements specific to vias in the SPB16.3 release of Allegro PCB Editor have been introduced. The are called use via region and stacked via support.
Use Via Region
Many times you need to restrict usage of specific vias in a region. Allegro PCB Router has been enhanced to allow via usage in a certain region.
The use_via rule has been enhanced to align with the Allegro via list functionality. The following objects…
- 22 Jun 2010
SoC and IP: MemCon 2010 Agenda. July 28, Santa Clara, California. Register Now.

archive

MemCon is coming up next month, on July 28 in Santa Clara, California. Here’s a list of presentations and panels you’ll see. But only if you register. Register here.

Memory Market Outlook
Recurring Memory: Cycle Gathers Profit Momentum after Huge 2008 - 2009 Losses Lane Mason, Memory Market Analyst

Emerging DRAM Technology: A 3D Perspective Arun Kamat, VP Marketing
Hynix

Designing High Efficiency DDR3…
- 22 Jun 2010
Verification: DAC360: Photo blog of DAC 2010 in Anaheim, CA

jvh3

Click here or on the image below to go to the annotated photo blog of DAC 2010.

Images and notes include highlights from:
* The Cadence and OVM/UVM booths
* Sites around the show floor
* Things outside of the expo, including panels, papers, and presentations (Yes, there is more to DAC than booths!)
Enjoy!
Joe Hupcey III

P.S. Some images from "Day 0" of DAC are posted here.

On Twitter: @jhupcey, http://twitter.com/j…
- 22 Jun 2010
SoC and IP: Xilinx unleashes triad of low-power, 28nm FPGA families with very promising characteristics for memory interfacing

archive

Today, Xilinx unveiled three new series of FPGAs all based on 28nm process technology from Samsung and TSMC. The three families are called the Virtex-7, Kintex-7, and Artix-7 series. All three FPGA families feature programmable I/O drivers with I/O voltages as low as 1.2V, which theoretically permits the use of all advanced, single-ended SDRAM interfaces such as the low-voltage LPDDR2 and high-speed DDR3-2133 memory interfaces…
- 21 Jun 2010
SoC and IP: ProMOS in Taiwan brings up Elpida 63nm process, successfully builds 1-Gbit DDR3 SDRAMs

archive

Taiwan DRAM maker ProMOS has just announced successful fabrication of 1-Gbit DDR3 SDRAMs using Elpida’s 63nm (a 65nm shrink) fabrication process, transferred to ProMOS under a strategic partnership between the two companies that was initiated at the end of 2009. The 63nm process is up and running at ProMOS’ Taichung fab and the first trial lot of devices meets parametrics, signifying successful transfer of the 63nm process…
- 21 Jun 2010
Verification: DAC Cabbie Taught Me All I Need to Know About Verification

Adam Sherer

Confidence from competence. Measurement through metrics. Sell without selling. These are the pearls I learned from my cab driver on the way home from DAC. Aside from the core truths they convey, they clearly define the top three verification items I saw at 47th DAC in Anaheim this year.
Topping my list is the surging interest in OVM as it matriculates into the Accellera UVM. The OVM/UVM booth at DAC picked up nearly 800…
- 21 Jun 2010
SoC and IP: Samsung’s 512 Gbyte SSD pushes SATA 3 Gbps to the limit with “30nm class” Toggle NAND Flash chips

archive

Samsung just announced that it will be in volume production with a high-speed, 512 Gbyte SSD next month. The company rates the drive’s sequential read and write performance at 250 Gbytes/sec and 220 Gbytes/sec respectively. According to Samsung, these performance numbers come from a combination of 32-Gbit toggle-mode NAND Flash chips (produced in a “30nm class” process announced at the end of 2009) and Samsung’s Flash…
- 18 Jun 2010

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