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RF Engineering: New Fast Envelope in MMSIM10.1 is *Really* Fast and Accurate!

Tawna

Traditionally, envelope analysis is used to simulate circuits with modulated inputs.
Envelope analysis is much faster than transient simulation, and is used for simulating spectral regrowth.

Regular envelope analysis is "brute force" transistor-level...
- 15 Nov 2010
Verification: Open Mobile Summit -- What‘s Happening in the World of Applications

Steve Brown

I attended last week's Open Mobile Summit in San Francisco last week. This is a twice-a-year event, once here and once in London. The conference attracted over 600 attendees to discuss the world of mobile applications -- open mobile, to be precis...
- 15 Nov 2010
System, PCB, & Package Design : What's Good About Allegro GRE Planning? You’ll Need the SPB16.3 Release to See!

Jerry GenPart

This new SPB16.3 Global Route Environment (GRE) Plan Status and Router Status functionality will assist you in finding errors and is designed to make it easier to work with the router and obtain feedback from the router. It employs a Constraint Manager type spreadsheet interface with cells that are active. In other words, you can execute commands on the data found within the cells.

The Plan Status and Router Status forms…
- 10 Nov 2010
Verification: System Bring-Up - THE Critical Path in the System Development Process

Ran Avinun

The electronic industry is moving from hardware-defined products to software-defined and application-driven products. As a result, product differentiation shifts to software content while hardware platforms and their development processes increasingl...
- 9 Nov 2010
Verification: 2010 CDNLive Silicon Valley Photo Blog: Silicon Realization, ABV, OVM, MDV, Specman, Formal and More

jvh3

If you are running short on time and can't view all the videos of the 2010 CDNLive Silicon Valley in San Jose, CA on October 26 posted here: www.cadence.com/cdnlive/na/2010/pages/default.aspx consider this photo blog as your very own "Cliff Notes" version. Click here to go to the gallery.

Images and descriptive captions include highlights from:
* The main stage keynote presentations and panel discussion
* Verification…
- 9 Nov 2010
Verification: The Amazing Diversity of the SoC Conference

tomacadence

Although I attend a number of conferences and tradeshows each year, most of these are rather EDA-centric. But last week I was in Irvine for the eighth annual International System-on-Chip (SoC) Conference. It is a fairly small event -- more like a workshop in some ways -- with a single track over its two days. I do not believe that I have ever been to any conference with such a diverse range of topics in one track…
- 8 Nov 2010
System, PCB, & Package Design : Favorite Features of an IC Package Designer: Wirebonding

TeamAllegro

This is the fourth in a series of discussions we would like to open up regarding “favorite features” in an IC Packaging implementation design tool.While wirebond packages are nothing new, the challenges associated with package designs usi...
- 8 Nov 2010
Analog/Custom Design: SKILL for the Skilled: Making Programs Clear and Concise

Team SKILL

The SKILL programming language augments Cadence core tool functionality for Virtuoso and Allegro customers. It is also an important development tool for internal Cadence services organizations as well as Cadence product development groups. We see the value, power, flexibility, and elegance of the language as an enabling tool for customizing and enhancing design environments. These capabilities are made possible…
- 8 Nov 2010
SoC and IP: STT-MRAM -- from Seagate???

archive

On June 12, 1989, I flew to Minnesota from Denver, Colorado, picked up a rental car, and drove from Minneapolis to Bloomington to attend a special disk drive conference being held by the leading vendor of cutting-edge 5.25-inch hard disk drives--Imprimis--which was the disk-drive spinout subsidiary of Control Data Corporation (CDC). I had an ulterior motive on this trip: to get two of Imprimis’ 330Mbyte SCSI disk drives…
- 5 Nov 2010
Digital Design: CDNLive! Silicon Valley 2010: User Papers Explore Digital Implementation

BobD

I previously wrote about the general session of the 2010 CDNLive! Silicon Valley conference, focusing on what EDA360 means for Digital Implementation engineers. Today I wanted to share a little more about a couple of papers I co-presented along with Cadence customers. I enjoy co-presenting with customers where I, as a Cadence Applications Engineer, describe a piece of functionality in the system and then a customer…
- 4 Nov 2010
Verification: Using Scoreboards and Virtual Platforms for Software Verification

jasona

Today I'm running a guest article written by Henry Von Bank of Posedge Software, a Cadence Verification Alliance Partner. For some background refer to the interview I did with Henry back in November 2008. Henry has been working on advan...
- 3 Nov 2010
System, PCB, & Package Design : What's Good About Differential Pairs in Allegro Constraint Manager? See For Yourself in SPB16.3!

Jerry GenPart

There are a couple new Differential Pair (Diff Pair) capabilities available with the SPB16.3 Allegro PCB Editor Constraint Manager - Differential Pair Renaming and Dynamic Phase Control for Differential Pairs.
Differential Pair Renaming
Prior to the SPB16.3 release, library and model-defined differential pairs are automatically named based upon the member nets of the differential pair. However, you might want to rename…
- 3 Nov 2010
Verification: Verification Goldmine: 50 User Papers on Formal, Multi-Engine, and Assertion-Based Verification (ABV)

TeamVerify

With all due respect to our Tech Pubs writers, Solutions Architects, and contributors to this blog, nothing beats hearing the experiences of end users applying a given tool or methodology to their real world challenges. Fortunately, Team Verify has been blessed with a generous and prolific community of users who have taken the time to share their experiences in pure formal verification, multi-engine mixes of formal and…
- 2 Nov 2010
Verification: CDNLive! Silicon Valley 2010 in the Rear-View Mirror

tomacadence

Well, we all survived another very busy CDNLive! event last week. Since I posted a preview beforehand I would be remiss if I didn't let you know what happened. The bottom line is that this was a really good show, with more than forty talks covering a wide range of EDA and EDA360 topics. The majority of these were presented by customers, with some additional sessions from Cadence management and technical experts…
- 2 Nov 2010
Verification: User Views -- Migrating From FPGA-Based Prototyping to Palladium

Ran Avinun

In recent posting published by John Cooley on Deepchip.com, users compared FPGA-based prototyping systems to Palladium systems. I always like to read responses that reflect user views -- as we all know these are always more credible.I would like&nbsp...
- 2 Nov 2010
RF Engineering: Virtuoso APS Supports RF Analyses in MMSIM 7.2 and MMSIM 10.1

Tawna
A new multi-threading capability has greatly improved simulation speed for RF Designers!
In MMSIM7.2, we introduced APS for Harmonic Balance analyses (multi-threaded harmonic balance simulation).
In MMSIM10.1, we added support for APS in Shooting PSS...
- 29 Oct 2010
System, PCB, & Package Design : A Shorter, Predictable Design Cycle for Complex PCBs -- Electrical Constraint Sets (ECSets)

hemant

This is the first in a series of blogs focused on how you can make your design cycle predictable and shorter for PCB designs that are increasing in complexity. PCB designers have to deal with increased complexities while design teams are dispersed geographically, and the time to finish the design is continuing to shrink. Some of these PCB design trends are being fueled by the desire of consumers for smaller, cheaper…
- 29 Oct 2010
Digital Design: CDNLive! Silicon Valley 2010: What EDA360 Means to Digital Implementation Engineers

BobD

CDNLive! Silicon Valley 2010 -- our user's group meeting and more -- kicked off yesterday morning at the Fairmont Hotel in San Jose, California. It's been 2 years since the last CDNLive! (last year's event was online-only) where I captured this video of our Encounter software running though VPN/VNC on an iPhone. I was thinking this morning: How are we going to top that? What is going to be the thing I remember…
- 27 Oct 2010
Verification: The Increasingly Hazardous World of FPGA Verification

tomacadence

Last week saw the publication of two interesting blog posts regarding the growing challenges of FPGA verification, first from my buddy Dave Orecchio over at GateRocket and then from my Cadence colleague Steve Leibson. Both posts made the point that FPGA developers are increasingly facing the same verification issues as developers of non-programmable devices. This trend has been evident for quite a few years, but…
- 26 Oct 2010
Verification: CDNLive! -- Israel and the U.S.

Ran Avinun

The Cadence Design Network provides a great way to learn about the latest design and verification methodologies offered by Cadence, and the ways customers are using them. I had the pleasure to attend CDNLive! in Israel last week. For me, visting Isra...
- 25 Oct 2010
Verification: Android, Linaro, and 10 Other Useful Embedded Linux Links

jasona

The state of Minnesota is unofficially divided into two parts; The Cities and The Rest of the State. Of course, The Cities refers to the Twin Cities of St. Paul and Minneapolis. Outstate people from Grand Marias to New Ulm are happy to avoid the crow...
- 25 Oct 2010
Verification: e Templates and e Macros -- An Update for Specman Users

teamspecman

A couple of recent blogs have mentioned the feature of e templates, which was added to Specman relatively recently. If you are used to e macros -- the feature that has existed in the e language almost since forever -- you may wonder if it's not just the same concept in a different form. In other words, is it really essential to use templates, when you can use macros to achieve exactly the same result?
In some sense…
- 22 Oct 2010
SoC and IP: Apple boots HDD--completely out of the new MacBook Air notebooks. SSD is the only option

archive

Claiming that the move unifies Apple’s product line, Steve Jobs yesterday announced two new lightweight MacBook Air notebook computers. Significantly, neither HDD nor optical disk storage is an internal option for these two new laptops. SSD is the only storage on offer, with capacities from 64 to 256 Gbytes. Although Jobs claims that Apple placed the SSD “right on the motherboard,” the images he showed were of a small…
- 21 Oct 2010
Verification: Team Verify at CDNLive Silicon Valley Next Week – ABV, Formal, Multi-Engine Verification and More

TeamVerify

At next week's CDNLive! Silicon Valley in San Jose, California, Cadence will cover all aspects of our verification technologies and methodologies (the agenda for Day 1 is posted here, and the Day 2 techtorials here). Of course, Team Verify will be there to support any and all events related to assertion-based verification in general, and formal and multi-engine verification in particular. Here are the specific events…
- 20 Oct 2010
Verification: A Preview of Verification Sessions at CDNLive! Silicon Valley

tomacadence

As Cadence followers well know, our annual worldwide series of CDNLive! events is a big deal both for us and for our customers. We work hard to get the best talks into the program, combining customer case studies, technical updates from Cadence experts, and the occasional partner presentation. As you might imagine, we always receive more abstracts than we can fit into the slots available, which allows the program…
- 20 Oct 2010

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