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Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML

Transforming Chip Design with Cadence Cerebrus AI Studio

Cadence is transforming chip design with the launch of Cadence Cerebrus ® AI Studio…

Sean Kobayashi
• 1 min read
digital design , featured , agentic ai , designed with cadence , Cadence Cerebrus

Conformal AI Studio: Accelerated LEC/ECO/LP with AI/ML-Driven Enhancements

If you're a chip designer or verification engineer, you have likely spent countless…

David Stratman
• 5 min read
conformal , featured , Digital Implementation , Conformal AI Studio , AI/ML
Digital Design
Latest blogs

Training Insights Webinar: IR-Aware ECO Optimization Using Voltus and Tempus

This training webinar lets you investigate the IR-drop impact on timing and walked…

• 2 min read
ECO , Voltus IC Power Integrity Solution , Cadence training , Digital Implementation , Power Analysis , Tempus Timing Signoff Solution , IR drop , cadence learning and support

Training Insights – Want to Learn How to Test the Design and Its Need?

Why is Design for Testability (DFT) crucial for VLSI (Very Large Scale Integration…

• 2 min read
digital badge , DFT , Design for Test , training , training bytes , Cadence Modus DFT , online training , Test Automation

Voltus Voice: Elevate Your Power Signoff Approach Using 3D Vector Profiling

Performing vectored power analysis on localized high power consumption regions of…

• 5 min read
switching power , Silicon Signoff and Verification , Voltus IC Power Integrity Solution , power consumption , Power Signoff , Power Integrity , vector profiling

Training Insights Webinar: Designing a Complete Chip Using the RTL-to-GDSII Flow

Would you like to know how to design a complete chip using the RTL-to-GDSII flow…

• 2 min read
ECO , conformal , Static timing analysis , DFT , Silicon Signoff and Verification , Genus , Tempus , logic Equivalency Checking , STA , Floorplanning , RTL-to-GDSII , training , webinar , training bytes , digital implementation , Digital Implementation , Innovus , RTL2GDSII , Synthesis , stylus , Tempus Timing Signoff Solution , five minute tutorial , physical implementation , Modus ATPG

How AI-Based Cadence Cerebrus Improves Performance and Reduces Area for TI

Microcontrollers (MCUs) have become the backbone of embedded designs and are fueling…

• 5 min read
cerebrus , PPA Improvement , Cadence Cerebrus

Training Insights - Unveil the Track to Become an Expert in Synthesis

Are you wondering what is the next step to becoming an expert in the synthesis using…

• 2 min read
digital badge , conformal , Genus , advanced synthesis , training bytes , Synthesis , stylus , online training , Online Support

Leveraging the Power of Cadence Cerebrus Apps to Improve PPA and Productivity

The world of semiconductors is experiencing a golden era of innovation and technological…

• 5 min read

Accelerating Advanced-Node Technologies with the Tempus DRA Suite

In today's technology-driven world, there is an increasing need for semiconductor…

• 4 min read
Modeling Analysis , Tempus DRA Suite , featured , Design Robustness , Tempus , signoff

Training Insights — 3D-IC: What Is Silicon Interposer?

Moore’s Law is slowing down due to rising complexity with advanced nodes (such as…

• 3 min read
High-Level Synthesis , Silicon Signoff and Verification , 3D Heterogenous Integration , integration , package , online courses , C4 Bumps , Integrity 3D-IC Platform , 3D-IC , 2.5DiC , Latest Technologies , 3DIC , TSV , Cadence training , training bytes , Digital Implementation , TSVs , Innovus , moore's law , 3D-IC Technology , interposer , VLSI Design , 3D-IC High_Level_Presentation

Training Webinar: A Revolutionary Approach to Optimizing Chip Design

Please join me, Cadence Training and Application Engineer Krishna Atreya, for this…

FormerMember • 1 min read

Voltus Voice: Multi-Chiplet Marvels - Stepping into the 3D-IC Signoff Realm

Read this blog to understand how the Voltus 3D-IC power and IR signoff flow helps…

• 4 min read
system in package , Voltus IC Power Integrity Solution , Integrity 3D-IC Platform , 3DIC , system planning , EMIR , Multi-Chiplet Design

Training Insights - Want to Implement Functional Safety to Make the Design Robust…

Reliable semiconductors will be crucial to the success of future safety systems.…

• 1 min read

Learn How Cadence and Arm Are Building the Future of Infrastructure

With over 30 years of experience in the semiconductor industry, Cadence and Arm Are…

• less than a min read
digital design , artificial intelligence , Generative AI , designed with cadence , Cadence Cerebrus , machine learning , Digital Implementation , GenAI , chip design automation , AI/ML , ARM , AI

Training Webinar: IR-Aware ECO Optimization Using Voltus and Tempus Solutions

This blog post draws your attention towards an upcoming training webinar "IR-Aware…

• 1 min read
Static timing analysis , Silicon Signoff and Verification , Voltus IC Power Integrity Solution , Cadence training , Digital Implementation , Tempus Timing Signoff Solution , IR drop

Keep Up with the Revolution—Cadence Cerebrus Training

Can you imagine specifying your design goals and having a tool intelligently optimize…

FormerMember • less than a min read

3D-IC: The Future of Integrated Electronics Is the Future of Electronics Itself

According to Gordon E. Moore, “The future of integrated electronics is the future…

• 2 min read
3D-IC , 2.5DiC , IC layout , 3DIC RAKs , training bytes , C4 Bump , Digital Implementation , TSVs , Innovus , 3D-IC Technology , 3DIC vs 2.5DIC , interposer , heterogenous integration , RAKs , 3D-IC High_Level_Presentation , IC design , 3DIC References

Joules RTL Design Studio: Accelerating Fully Optimized RTL

Cadence announced Joules RTL Design Studio today at CadenceLIVE Japan 2023, a new…

• 2 min read
digital design , RTL diff , featured , RTL synthesis , RTL restructuring , PPAC , Digital Implementation , lint checker , RTL design , RTL debugging , RTL analysis , Joules RTL Design Studio

Recording Now Available: Intro to Genus iSpatial Synthesis Flow Webinar

With advanced-process nodes, a standard cell's physical delay, net delay, and congestion…

• 1 min read
Genus , featured , Floorplanning , training , webinar , ispatial , Placement , Cadence Support Portal , physical implementation , cadence learning and support

Voltus Voice: Multi-Chiplet Marvels - Harnessing Power by Early Analysis of 3D-IC…

Read this blog to get a chip-centric perspective on how to perform power integrity…

• 5 min read
Early Rail Analysis , system in package , Voltus IC Power Integrity Solution , Innovus Implementation System , Integrity 3D-IC Platform , 3D-IC , IRdrop , system planning , Multi-Chiplet Design

Training Insights - RTL-to-GDSII: Creativity Meets Engineering in Chip Design

In this blog post, we will explore how the RTL-to-GDSII flow brings together the…

• 3 min read
High-Level Synthesis , Physical verification , ECO , conformal , IMC , conformal lec , DFT , Genus , Post layout simulations , Routing , Freshers , ASIC flow , LEC , logic Equivalency Checking , Post synthesis simulations , STA , Floorplanning , RTL-to-GDSII , EDA , NanoRoute , training , Gate level simulations , Logic Design , coverage analysis , training bytes , clock tree synthesis , Freshly Graduate , Digital Implementation , Encounter Digital Implementation , physical design , creativity , xcelium , Synthesis , RTL Code , signoff , Placement , RTL design , Gate level netlist , Tempus Timing Signoff Solution , timing signoff , physical implementation , vManager , internship , Modus ATPG , verification

Voltus Voice: 3 Commands You Should Know to Debug Power Using Voltus

Accuracy of power calculated by the design tool is controlled by the correctness…

• 4 min read
Low Power , Voltus IC Power Integrity Solution , Power Signoff , power debug , Power Analysis , power optimization

How Do You Solve a Problem Like Clock Tree Synthesis?

The Clock Concurrent Optimization (CCOpt) technology in Innovus merges timing optimization…

• 1 min read
featured

Voltus Voice: Voltus-Celsius Integration for System Analysis —The Super Simple W…

Learn how the Voltus-Celsius integrated solution can help you achieve faster system…

• 3 min read
Celsius Thermal Solver , Silicon Signoff and Verification , Voltus IC Power Integrity Solution , 3D-IC , Signoff Analysis , Power Integrity , co-simulation , electrical-thermal , Thermal Integrity

Planning a Long Drive this Summer? A Look Behind the Safety of Your Car’s Electr…

We know you are particular about your road safety while driving your automobile.…

• 3 min read
Automotive , gui , functional safety , USF , midas

Training Insights Webinar: Introduction to the Genus iSpatial Synthesis Flow: Registrations…

What Is this Webinar About? Please join me, Neha Joshi, Sr. Principal Education…

• 2 min read
featured , Genus Webinar , ispatial , Cadence Support Portal , Cadence support , cadence learning and support

Voltus Voice: How Voltus RTL Power Analysis Enables Sustainable Innovation

This blog discusses how the Voltus RTL power analysis flow reduces power consumption…

• 5 min read
Low Power , Silicon Signoff and Verification , featured , Voltus IC Power Integrity Solution , sustainable design , RTL-to-GDSII , sustainable development goals , Digital Implementation , Power Analysis

“How Do You Eat an Elephant?”

“There is only one way to eat an elephant, a bite at a time,” is a quote often attributed…

• 1 min read
digital badge , learning , Support , training , training bytes , Innovus

Training Insights - It's Time to Recharge your Design Results with Double Benefits…

With highly advanced technology, the real designs are getting complex, complicating…

• 2 min read
digital badge , scan , DFT , Genus , IEEE 1500 , training , wrapper , live
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