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Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML

Transforming Chip Design with Cadence Cerebrus AI Studio

Cadence is transforming chip design with the launch of Cadence Cerebrus ® AI Studio…

Sean Kobayashi
• 1 min read
digital design , featured , agentic ai , designed with cadence , Cadence Cerebrus

Conformal AI Studio: Accelerated LEC/ECO/LP with AI/ML-Driven Enhancements

If you're a chip designer or verification engineer, you have likely spent countless…

David Stratman
• 5 min read
conformal , featured , Digital Implementation , Conformal AI Studio , AI/ML
Digital Design
Latest blogs

Arm Applies Cadence Cerebrus to Optimize PPA of Next-Gen 3nm Core Implementation

The world’s insatiable demand for data and its processing is leading to more innovations…

• 6 min read
Neoverse V2 , PPA Improvement , Cadence Cerebrus , Cadence and Arm Collaboration

Let's Unveil the Power of Cloning and Rewiring for Your Scan-Inserted Design!

Are you fascinated by clones? We can bring the same excitement to your design flow…

• 2 min read
scan , DFT , Genus , clone , IEEE 1500 , wrapper

Training Insights - Wondering How to Upgrade Your Skills? We Asked ChatGPT

Which courses are important for new college graduates and working professionals to…

• 6 min read
digital badge , Conformal ECO Designer , conformal , Low Power , Genus , Cadence blogs , online courses , Tempus , 3D-IC , Signoff Analysis , tutorial , STA , Power Integrity , Cadence Online Support , Floorplanning , RTL-to-GDSII , Joules , training , ccopt , Voltus , Cadence training , training bytes , digital implementation , digital , Innovus , Power Analysis , Synthesis , IR drop , physical implementation

Voltus Voice: Voltus-Innovus Integration Avoids Potential Power-Signoff Issues

This blog highlights the benefits of Voltus-Innovus integration for power-grid optimization…

• 4 min read
Innovus Power Integrity , Silicon Signoff and Verification , Voltus IC Power Integrity Solution , badge , training , Digital Implementation

Training Insights - What's Your Weekend Plan? How About an Interactive Tour of the…

Well, we know you are busy, but it's time to develop your expertise in the synthesis…

• 3 min read
digital badge , Genus , training bytes , Synthesis , online training , Online Support

Training Insights – Webinar – Transforming your Timing Signoff Experience with Tempus…

This blog post describes the latest innovations in the Cadence®︎ Tempus™︎ Timing…

• 2 min read
Digital Implementation , Tempus Timing Signoff Solution , cadence learning and support

Voltus Voice: Dulce Domum and Happy Holidays!

A recap of the power integrity posts in the Voltus Voice blog series through 2022…

• 5 min read
Silicon Signoff and Verification , Voltus IC Power Integrity Solution , 3D-IC , Power Integrity , Power-Efficient Design , hierarchical power integrity analysis , Thermal Integrity , Power Analysis , vector profiling , vectorless

Voltus Voice – How to Step Up Your Game with Target Power Vectorless Dynamic EMIR…

Check out this blog to learn how you can perform accurate modelling of localized…

• 5 min read
Voltus IC Power Integrity Solution , Power Target Vectorless EMIR , Power Integrity , Power-Efficient Design , Digital Implementation , Power Analysis , signoff , vectorless , dynamic power

Training Insights - RTL-to-GDSII Lab: Just One Click to Increase Your Confidence…

Are you struggling to run the RTL2GDSII labs? Want to speed up your learning time…

• 3 min read
Physical verification , ECO , conformal , IMC , Static timing analysis , DFT , Silicon Signoff and Verification , Genus , hold , rail analysis , Tempus , Routing , ASIC flow , LEC , drv , STA , Setup and Hold Analysis , Floorplanning , RTL-to-GDSII , Logic Design , coverage analysis , xrun , setup , logic equivalence checking , digital implementation , GDSII export , Innovus , digital full flow , physical design , Timing analysis , rtl2gds2 , Power Analysis , xcelium , CTS , RTL2GDSII , Synthesis , Placement , Tempus Timing Signoff Solution , IR drop , physical implementation

Knowledge Booster Training Bytes - In-Design Pegasus Signoff Verify Design (SVD)

In-Design Pegasus Signoff Verify Design (SVD) integrates Pegasus Signoff and Pegasus…

• 5 min read
Pegasus Verification System , pegasus , DRC , training bytes , Innovus , signoff , silicon signoff , RAKs , verification

Training Insights - What Is IR drop? Is it Possible to Run IR-drop Analysis Using…

IR drop is the difference between two endpoints of the conducting wire during a current…

• 3 min read
rail analysis , Power Signoff , current density , Power Integrity , Cadence Online Support , training , Logic Design , training bytes , Digital Implementation , Innovus , Power Analysis , IR drop , power

Training Insights - Dude, Where's My Software?

When you go to download the latest version of Innovus, Genus or Joules our Cadence…

• 1 min read
Silicon Signoff and Verification , Genus , Joules , Innovus , Synthesis , physical implementation

Voltus Voice: Voltus-Sigrity Collaboration Fuels System Innovation

Learn how the Voltus-Sigrity X integrated solution can help you achieve faster system…

• 3 min read
Voltus IC Power Integrity Solution , Power Signoff , 3D-IC , Signoff Analysis , Power Integrity

How Does Marvell Improve Productivity and TapeOut Time with Automated ECO Implementation…

How to fix the bugs after RTL freeze and perform ECO. Learn how Automated ECO Implementation…

• 3 min read
ECO , Conformal ECO Designer

Training Insights – Webinar – Transforming your Timing Signoff Experience with Tempus…

This webinar encourages you to learn and apply the latest innovations in the Cadence…

• 3 min read
Static timing analysis , Silicon Signoff and Verification , Digital Implementation , Tempus Timing Signoff Solution

HLS for AI/ML Models: TensorFlow to RTL

Artificial Intelligence (AI) plays a key role in semiconductors to meet the challenging…

• 3 min read
Stratus HLS , Genus

Voltus Voice: How to Find Functional Power Vectors that Matter Quickly

Vector profiling enables ASIC designers to quickly identify areas with maximum activity…

• 6 min read
switching power , Low Power , Voltus IC Power Integrity Solution , power consumption , Power Signoff , Power Profile , Digital Implementation , switching activity , Power Analysis , vector profiling

Relax in Summer with Cooler IC chips and Ice-Cream! Do you want to Explore the Recipe…

Are you passionate about cooking? Err... Don't think it is a regular cooking class…

• 1 min read
Low Power , Genus , IEEE 1801 , UPF , Synthesis

Resolve Congestion and Physical Design Challenges Using Cadence Support and RAKs

Physical design challenges such as congestion, routing, on-chip variation (OCV),…

• 5 min read
routing congestion , OCV , clock tree synthesis , Innovus , Rapid Adoption Kits , Cadence support

Voltus Voice: Five Great Features to Enhance Your Full-Chip Power Signoff

This blog shares five great features to unlock the potential of your digital designs…

• 5 min read
Celsius Thermal Solver , scan chain , featured , power density , Voltus IC Power Integrity Solution , Power Signoff , Signoff Analysis , Power Integrity , learning , Power-Efficient Design , noise analysis , vector-based , Thermal Analysis , Power Analysis , vector profiling , vectorless , dynamic power

SSV 22.1 Base Release Now Available

The Silicon Signoff and Verification (SSV) 22.1 release is now available for download

• 3 min read
Cadence blogs , Voltus IC Power Integrity Solution , 3D-IC , Power Integrity , multi-die design , Timing analysis , Power Analysis , Aging-Aware STA , silicon signoff , Tempus Timing Signoff Solution

Training Insights – Design Robustness Analysis Application: Aging-Aware STA

This blog post describes the phenomenon of Aging, the factors affecting it, and how…

• 2 min read
Timing analysis , aging , Liberate , silicon signoff , Tempus Timing Signoff Solution

Brain on Fire - AI/ML Art Creation

No matter how you feel about the topic, we're definitely past the turning point in…

FormerMember • 1 min read
Silicon Signoff and Verification , Genus , Tempus , cerebrus , Digital Implementation , Innovus

RTL-to-GDSII Flow: I Am Not a Tool but Can Help You Implement Your Entire Design…

Passion motivates and helps you pursue it further, but gaining expertise requires…

• 4 min read
ECO , conformal , Static timing analysis , VLSI , scan , DFT , Integrated Metrics Center , Genus , featured , Cadence blogs , GDSII , code coverage , Tempus , Functional Verification , Gate level simualtion , ASIC flow , gds , LEC , Signoff Analysis , RTL , SDF , STA , Cadence Online Support , Floorplanning , RTL-to-GDSII , training , Logic Design , xrun , Equivalence Checking , Layout , digital flow , Digital Implementation , Innovus , physical design , Timing analysis , Cadence Education Services , ATPG , xcelium , RTL2GDSII , Synthesis , signoff , physical implementation , Design specifications , verification , cadence learning and support

What's Behind the 5% Die-Area Shrink and 12% Power Saving by MediaTek?

Leveraging Cadence Cerberus AI-Enabled Chip Optimization Solution MediaTek Achieves…

• 3 min read
Intelligent chip explorer , featured , Cadence Cerebrus , Digital Implementation , AI

Training Insights - Achieving a Holistic Power-Aware Design by Getting Low-Power…

This blog post mentions the Cadence Low Power Solution, a design-to-signoff methodology…

• 2 min read
Low Power , digital implementation , Innovus

Voltus Voice: Overcoming Design Challenges Using Voltus Documentation—The Definitive…

This post facilitates easy access to the Voltus Help and Documentation through the…

• 3 min read
digital badge , Silicon Signoff and Verification , Voltus IC Power Integrity Solution , training bytes , Digital Implementation , Cadence Education Services

Scan Mapping, Expectation Versus Reality? It's Time to Grab All the Scan Cells!

We all look for 100% perfection and want to turn our dreams (expectations) into reality…

• 1 min read
scan , DFT , Genus , Synthesis
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