Featured

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML

Transforming Chip Design with Cadence Cerebrus AI Studio

Cadence is transforming chip design with the launch of Cadence Cerebrus ® AI Studio…

Sean Kobayashi
• 1 min read
digital design , featured , agentic ai , designed with cadence , Cadence Cerebrus

Conformal AI Studio: Accelerated LEC/ECO/LP with AI/ML-Driven Enhancements

If you're a chip designer or verification engineer, you have likely spent countless…

David Stratman
• 5 min read
conformal , featured , Digital Implementation , Conformal AI Studio , AI/ML
Digital Design
Latest blogs

Power Is HOT and Touches Everything and Everybody! But the Challenge Is To Deal With…

Low-Power synthesis is one of the important stages in the full IC flow. Here, you…

• less than a min read
Low Power , Genus , Digital Implementation , Synthesis , power optimization

Are You Planning To Synthesize Your Design? Do You Want To Explore the Synthesis…

A Logic Synthesis is a process of optimizing the design's area, timing, and power…

• less than a min read
Genus , Flows , Logic Design , Optimize , Synthesis

Chris, Kris, Cris, Your Name, My Name; Does How You Spell the Name Matter to Conformal…

No matter how your name is spelt in different countries, and how they say it, once…

FormerMember • 1 min read
digital badge , conformal , training bytes , online training

Do You Want to Explore Instances in Genus Synthesis Solution Layout GUI?

What comes to your mind when we say Genus Layout GUI (Graphical User Interface)?…

• less than a min read
Genus , gui , place and route , highlighted objects , physical implementation

Voltus Voice: Simplifying Power Signoff for HPC Systems: Super-Charge your Power…

In the first post of our " Simplifying Power Signoff for HPC Systems" blog series…

• 4 min read
Silicon Signoff and Verification , Voltus IC Power Integrity Solution , Power Signoff , Cycle Accurate Power Estimation , Event-Based Power Analysis , Power Analysis

Floorplanning Frustrations Got You Down? Help Is on the Way!

This post describes a channel of videos created to show how to floorplan a design…

• less than a min read
Floorplanning , Innovus

Mitigating Congestion, CTS, OCV and Other Challenges using Cadence Tools and Sup…

With the shrinking gemoetries and data-intensive endeavours of the upcoming industries…

• 6 min read
debug , Routing , Unconstrained Path , congestion , OCV , SOCV , RAKs

Voltus Voice: Early Power and Thermal Integrity Analysis in 3D-ICs - Why it Really…

Learn how to navigate through the challenges of power and thermal integrity analysis…

• 2 min read
Celsius Thermal Solver , system in package , Voltus IC Power Integrity Solution , Integrity 3D-IC Platform , 3D-IC , Power Integrity , Thermal Integrity , Multi-Chiplet Design

Voltus Voice: Hierarchical Power Integrity Analysis—Why xPGV Modeling Is the Designer…

In the final part of our "Hierarchical Power Integrity Analysis" blog series, we…

• 4 min read
Voltus XM , Silicon Signoff and Verification , Voltus IC Power Integrity Solution , xPGV models , Power Integrity , hierarchical power integrity analysis , IRdrop , Extreme Modeling , Full-Chip

Adopting a Faster, More Efficient Path to Multi-Chiplet Design

Gone are the days when process shrinking was considered as the primary driver of…

• 3 min read
chiplets , 3D-IC , Integrity , Thermal Integrity , system planning , Multi-Chiplet Design

Is your Compression Technique Unified? Wanna Explore?

Scan compression is critical for addressing the rapid rise of test costs without…

• 1 min read
scan , DFT , compression , Genus , Synthesis

Voltus Voice: Playback 2021 - Power Integrity Blogs At a Glance

A recap of the power integrity posts in the Voltus Voice blog series through 2021…

• 3 min read
Silicon Signoff and Verification , Voltus IC Power Integrity Solution , electrostatic discharge , resistance analysis , hierarchical power integrity analysis , Digital Implementation , rush current analysis

Pegasus: Get your Wings: Pegasus Results Viewer- LVS

In our previous blog we introduced Pegasus Results Viewer (Pegasus RV) and gave detailed…

• 4 min read
Pegasus Verification System , Physical verification , Pegasus RV , ERC , Pegasus Results Viewer , Extraction , pegasus , LVS , SCD , ISL , signoff , Pegasus LVS RV

Voltus Voice: ESD Analysis Task Assistant: Your Key to 'Getting Started'

This blog discusses the implementation of task assistant for the Voltus ESD analysis…

• 4 min read
Silicon Signoff and Verification , Voltus IC Power Integrity Solution , ESD reports , Power Signoff , electrostatic discharge , current density , Power Integrity , ESD

Voltus Voice: Hierarchical Power Integrity Analysis—Everything You Need to Know About…

In part 2 of our "Hierarchical Power Integrity Analysis" blog series, we discuss…

• 5 min read
Voltus XM , Silicon Signoff and Verification , Voltus IC Power Integrity Solution , xPGV models , Power Integrity , hierarchical power integrity analysis , IRdrop , Extreme Modeling , Full-Chip

Voltus Voice: 6 Tips to Jump-start Your Voltus Stylus Migration Journey

Cadence Stylus UI streamlines the RTL-to-Signoff design flow, bringing all the Cadence…

• 5 min read
Voltus IC Power Integrity Solution , Tempus , Signoff Analysis , Digital Implementation , Innovus , stylus

Do you want to Flaunt your Expertise? Grab the Digital Badge Today!

When you achieve the credit for proficiency, do you want to show it to the world…

• 1 min read
Genus , exam , badge , Joules , Synthesis

Voltus Voice: Hierarchical Power Integrity Analysis—The Quest for Accelerating Power…

To help you tackle contemporary challenges related to extremely large design power…

• 4 min read
Voltus XM , Silicon Signoff and Verification , Voltus IC Power Integrity Solution , xPGV models , Power Integrity , hierarchical power integrity analysis , IR drop , Extreme Modeling , Full-Chip

Pegasus: Get your Wings: Pegasus Results Viewer

You will agree with me that the earlier the bugs are caught the better it is for…

• 4 min read
Pegasus Verification System , Pegasus RV , Pegasus Results Viewer , pegasus , Pegasus DRC RV

Glitch?? Do Not Let It Impact Your Design Power!!

A glitch, although, is an unnecessary signal transition in your design. But its impact…

• 1 min read
Low Power , RTL , Joules , glitch , Power Analysis , power optimization

Conformal Low Power Verification

Learn to verify low-power designs using Conformal ® Low-Power Verification. We've…

FormerMember • less than a min read

Voltus Voice: Full-Chip Resistance Analysis – The Holy Grail of Power Grid Verif…

Do you want to determine the weak spots in your power grid network at the start of…

• 6 min read
Silicon Signoff and Verification , Voltus IC Power Integrity Solution , power grid , Least-Resistive Path , Power Integrity , resistance analysis , IR drop , Full-Chip

Three Quick Ways to Get Up to Speed with Innovus 21.1 with Stylus Common UI

Hello Digital Designers, Innovus 21.1 released a few weeks ago and you might be…

• 1 min read
place and route , Digital Implementation , Innovus

Pegasus: Get your Wings: Pegasus Run Controls

Have you ever been in a situation where the run has started and you realize that…

• 4 min read
Pegasus Verification System , Run Control Commands , pegasus , Pegasus Run Control , signoff

Voltus Voice: Unleashing the Power of Intelligent System Design Strategy - A chat…

In this blog, Rajat Chaudhry (Product Management Director of Voltus) tells us how…

• 9 min read
Innovus Power Integrity , Silicon Signoff and Verification , Voltus IC Power Integrity Solution , hierarchical power integrity analysis , Digital Implementation , Multiphysics System Analysis , Tempus Power Integrity

Have You Encountered Any Error/Warning During Scan Insertion in Genus? Do You Want…

Design for Test (DFT) techniques provide measures to test the manufactured device…

• 1 min read
scan , DFT , Genus , warning , error

A Proven Way to Simulate High-Frequency Electro-Magnetic Effects Using Quantus Extraction…

Cadence offers multiple electromagnetic (EM) extraction technologies to model the…

• 3 min read
Extraction , quantus rlck , Quantus

Voltus Voice: Demystifying ESD—Charting Your Way through Voltus ESD Reports

In the concluding blog of our "Demystifying ESD" series, we walk you through the…

• 6 min read
Silicon Signoff and Verification , electromigration , Voltus IC Power Integrity Solution , ESD reports , electrostatic discharge , current density , Power Integrity , Innovus , clamp , bump
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