Featured

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML

Transforming Chip Design with Cadence Cerebrus AI Studio

Cadence is transforming chip design with the launch of Cadence Cerebrus ® AI Studio…

Sean Kobayashi
• 1 min read
digital design , featured , agentic ai , designed with cadence , Cadence Cerebrus

Conformal AI Studio: Accelerated LEC/ECO/LP with AI/ML-Driven Enhancements

If you're a chip designer or verification engineer, you have likely spent countless…

David Stratman
• 5 min read
conformal , featured , Digital Implementation , Conformal AI Studio , AI/ML
Digital Design
Latest blogs

Voltus Voice: Demystifying ESD—Charting Your Way through Voltus ESD Reports

In the concluding blog of our "Demystifying ESD" series, we walk you through the…

• 6 min read
Silicon Signoff and Verification , electromigration , Voltus IC Power Integrity Solution , ESD reports , electrostatic discharge , current density , Power Integrity , Innovus , clamp , bump

SSV 21.1 Base Release Now Available

The Silicon Signoff and Verification (SSV) 21.1 release is now available for download…

• 3 min read
Celsius Thermal Solver , Temperature Map , Voltus IC Power Integrity Solution , 3nm , Power Integrity , Power Targets , silicon signoff , Tempus Timing Signoff Solution , Extreme Modeling

Do You Know DFT Violations Can Be Debugged Using Genus GUI? Excited to Explore?

Design for Test (DFT) techniques provide measures to comprehensively test the manufactured…

• less than a min read
scan , DFT , Genus , gui , debug , Digital Implementation , Violations , Synthesis

What’s Inside the GUI-Based Timing Report in Genus? Want to Explore?

Timing closure is one of the most crucial steps of a digital design. Therefore, to…

• 1 min read
report , Genus , gui , timing debug , Timing Optimization , debug report , Synthesis

Pegasus: Get Your Wings: Strong Immunity Makes Pegasus Fault Tolerant

We all know the importance of good immunity and how a good immune system makes you…

• 1 min read
Pegasus Verification System , Fault Tolerance , pegasus , signoff , silicon signoff

Low-Power Implementation Training Videos

This blog post describes the Low Power Implementation Flow and IEEE 1801 basic terminologies…

• 1 min read
Low Power , Digital Implementation , Innovus , Power Analysis

Voltus Voice: Demystifying ESD — 5 Types of Checks to Bump up Your ESD Protectio…

This blog discusses the different Voltus electrostatic discharge (ESD) checks in…

• 4 min read
effective resistance , Silicon Signoff and Verification , electromigration , Voltus IC Power Integrity Solution , Power Signoff , electrostatic discharge , current density , Power Integrity , Full-Chip , ESD

Verifying Design Changes Does Not Have to be Difficult and Tedious — Make it Easier…

You put your design through a multitude of tools for various transformations. Going…

FormerMember • less than a min read
conformal , formal , Logic Design , Equivalence Checking , Digital Implementation , verification

Library Characterization Tidbits: Define Measurements to Suit Your Characterization…

Do you have a requirement to specify measurements that are not default while performing…

• 3 min read
memory characterization , define_measure , Liberate MX , Library Characterization Tidbit , Liberate Characterization Portfolio

Pegasus: Get Your Wings: Virtuoso/Pegasus In-Design Signoff

The beauty of Pegasus is that it doesn’t only work excellently in standalone mode…

• 2 min read
Pegasus Verification System , Interactive SignOff Fill , pegasus , Pegasus Interactive , Density analysis , design for manufacturing

iSpatial: Next-Generation Common Physical Optimization Flow

With advanced-process nodes, a standard cell's physical delay, net delay, and congestion…

• 1 min read
Genus , Logic Design , Synthesis , ispatial , physical implementation

Voltus Voice: Demystifying ESD — Four Simple Steps to Run ESD Analysis Full-Chip…

This blog post outlines four simple steps for analysis of your electrostatic discharge…

• 5 min read
effective resistance , Silicon Signoff and Verification , Power Signoff , electrostatic discharge , current density , Power Integrity , Voltus , Full-Chip , ESD

Library Characterization Tidbits: Importance of Noise Analysis and the Role that…

The hustle bustle of the cities is only an example of the external noise, which we…

• 5 min read
CCSN characterization , CCSN , Liberty Variation Format , Reference-based modeling , cross coupled capacitance , characterization , composite current source noise , noise in digital circuit , CCS Noise , Library Characterization Tidbit , channel connected blocks , coupling cap , Liberate , noise propagation , Liberate Characterization Portfolio , Stage-based modeling , CCB , timing

Understanding Clock Gating Report and Cells

Hi everyone, Are you interested in reducing the power dissipation of your design…

• 2 min read
digital badge , blended training , Genus , training bytes , Digital Implementation , online training , cadence learning and support

Voltus Voice: Power-Saving Chip Design Is Not a Choice; It’s a Necessity

A blog on how the Voltus power-gating analysis solution enables engineers to address…

• 5 min read
Low Power , Silicon Signoff and Verification , static power , Voltus IC Power Integrity Solution , low-power technique , power gating , Power Integrity , rush current analysis , Innovus

Library Characterization Tidbits: Recovering from Failures in the Multi-PVT Characterization…

Ever wondered what should you do if any arc, cell, or PVTs failed in a characterization…

• 4 min read
Liberate Trio Characterization , Multi-PVT , Recharacterize , library characterization , Library Characterization Tidbit , Digital Implementation , PVT corners , failed arcs , Liberate Characterization Portfolio , recovery flow

All You Need to Know about Application Engineering in EDA

"How many tape-outs have you done?" asked the design manager of a semiconductor…

• 4 min read
application engineering , AE

Voltus Voice: Power Integrity and Signoff in 2020 – A Jog Down Memory Lane

Voltus TM IC Power Integrity Solution is a power integrity and analysis signoff solution…

• 2 min read
Silicon Signoff and Verification , electromigration , Voltus IC Power Integrity Solution , Power Integrity , IR drop

Do You Know Multibit Cells Could Help You Reduce Clock-Tree Power and Alleviate Wiring…

Hi everyone, Searching for yet another method to improve the QoR of your design…

• 3 min read
blended training , Genus , training bytes , Digital Implementation , online training , Cadence support

Library Characterization Tidbits: Bidding Adieu to 2020

This year all our “regular” routines were shaken up by COVID-19, which brought along…

• 2 min read
library characterization , Library Characterization Tidbit , Digital Implementation , Liberate Characterization Portfolio

Wondering What to Do During the Winter Staycation? How about Learning Something New…

We just recently released a training course that we are excited to tell you about…

• 1 min read
conformal , Genus , Tempus , modus , Voltus , Digital Implementation , Innovus

SSV 20.2 Base Release Now Available

The SSV 20.2 production release is now available for download at Cadence Downloads…

• 2 min read
Signoff ECO , Tempus PI , Timing analysis , Tempus Timing Signoff Solution

Voltus Voice: Worried about Fins Getting Self-Heated – Here’s SHE Analysis to the…

This blog highlights the key capabilities of the Voltus Self-Heat Effect (SHE) analysis…

• 2 min read
Silicon Signoff and Verification , electromigration , Voltus IC Power Integrity Solution , electrical-thermal , Digital Implementation , FinFET , self-heating effects , IR drop , Full-Chip

Pegasus: Get your Wings

Pegasus: Get your Wings is a blog series to showcase the capabilities of Pegasus…

• 2 min read
Pegasus Verification System , Physical verification , verification signoff solution , pegasus , DRC , design rule check , silicon signoff

Innovus Design Metrics: Visualize This!

To arrive at your targeted and optimized PPA, you will need to execute several Innovus…

• less than a min read
Innovus

Library Characterization Tidbits: Rewind and Replay - 3

This blog provides a summary of the last five blogs posted in the Library Characterization…

• 2 min read
constraint probes , minimum period arc , Liberate LV , encounter , library characterization , Liberate MX , Library Characterization Tidbit , Digital Implementation , Liberate Characterization Portfolio , library validation

Voltus Voice: Amplifying Your Chip Performance and Reliability to Solve Big-Data…

This blog introduces the new cloud-ready Extensively Parallel (XP) solution from…

• 5 min read
Silicon Signoff and Verification , Voltus IC Power Integrity Solution , Multi-Physics Technology , Power Integrity , cloud , parallel processing , distributed processing

Library Characterization Tidbits: Accelerating Signoff with Liberate - Installation…

This is the second edition of the Library Characterization Tidbits' mini-series that…

• 5 min read
Liberate Trio Characterization , tidbits , Liberate AMS , Liberate LV , Liberate Variety , library characterization , Liberate MX , Library Characterization Tidbit , Digital Implementation , Characterization Solution , Liberate , Liberate Characterization Portfolio
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