• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Forum - Thread List
  • Discussion

    Generate symbol thumbnail with pin names Locked

    7713 views
    0 replies
    Started over 3 years ago
    by AurelBuche
  • Discussion

    Controlling Window Placement in AWR Tool

    8874 views
    2 replies
    Latest over 3 years ago
    by Durward Bins
  • Discussion

    Is that possible to write an external function and call it in Virtuoso Verilog-A through VPI Locked

    9596 views
    2 replies
    Latest over 3 years ago
    by HiddenOnee
  • Discussion

    Running LVS: missing a simInfo section in it's CDF for the current simulator. Locked

    1139 views
    0 replies
    Started over 3 years ago
    by Yongqi Hu
  • Discussion

    Allegro 17.4.030 Hangs after Launch on Windows 10.

    10901 views
    3 replies
    Latest over 3 years ago
    by Dooba
  • Discussion

    Simulating an autonomous circuit in addition to a voltage source Locked

    10338 views
    4 replies
    Latest over 3 years ago
    by illaoi
  • Discussion

    Parasitics/LDE Setup Locked

    5985 views
    5 replies
    Latest over 3 years ago
    by Andrew Beckett
  • Discussion

    EMIR Setup Locked

    10320 views
    0 replies
    Started over 3 years ago
    by illaoi
  • Discussion

    RF filter using CPW lines with gnd plane Locked

    8903 views
    1 reply
    Latest over 3 years ago
    by David Webster
  • Discussion

    Adding CPU time as a measurement in ADE Assembler Locked

    14036 views
    14 replies
    Latest over 3 years ago
    by sidm
  • Discussion

    Unbound variable error when PCell SKILL code gets too long Locked

    11710 views
    3 replies
    Latest over 3 years ago
    by Andrew Beckett
  • Discussion

    How to find and print out the pins of schematic using skill Locked

    14713 views
    8 replies
    Latest over 3 years ago
    by Andrew Beckett
  • Discussion

    xrun simulation elaborates systemverilog real as binary Locked

    10073 views
    1 reply
    Latest over 3 years ago
    by JayBee
  • Discussion

    Simulation with CalcVal does not work in Global Optimization but it does in Single Run. Locked

    8596 views
    1 reply
    Latest over 3 years ago
    by Andrew Beckett
  • Discussion

    g_overwrite in ccpCopyDesign does not seem to work Locked

    8722 views
    2 replies
    Latest over 3 years ago
    by sbkuizlzl
<>

© 2026 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information