• Not Answered

  Forcing a net on a via when routing 0

  12648 views
  6 replies
  Latest over 3 years ago
  by Fredda
• Discussion

  follow up with find the location of a variable in schematic Locked

  9481 views
  1 reply
  Latest over 3 years ago
  by Andrew Beckett
• Discussion

  OrCAD - Tip of the Week: Graphical locking of objects you do not want to be changed

  2165 views
  3 replies
  Latest over 3 years ago
  by AyushD
• Discussion

  How to change default spacing between symbol's pins that auto-created from schematic Locked

  1883 views
  1 reply
  Latest over 3 years ago
  by Andrew Beckett
• Discussion

  PCB cooling with CFD analysis

  7335 views
  0 replies
  Started over 3 years ago
  by SimTech
• Not Answered

  Cannot load symbol 'CEC002C 0

  2506 views
  3 replies
  Latest over 3 years ago
  by myil17
• Discussion

  DEF formatting Locked

  9287 views
  1 reply
  Latest over 3 years ago
  by SSR
• Discussion

  Discrepancy in Stability Analysis Locked

  9771 views
  1 reply
  Latest over 3 years ago
  by FormerMember
• Discussion

  adding delay element to circuit Locked

  13298 views
  1 reply
  Latest over 3 years ago
  by FormerMember
• Discussion

  calculator plot function fail Locked

  9436 views
  1 reply
  Latest over 3 years ago
  by FormerMember
• Suggested Answer

  Generating pin pairs for Match Group members 0

  11699 views
  2 replies
  Latest over 3 years ago
  by Fredda
• Discussion

  report unused verilog packages Locked

  13366 views
  4 replies
  Latest over 3 years ago
  by Max Bjurling
• Discussion

  SystemVerilog generate loop does not compile modules defined inside loop Locked

  12604 views
  2 replies
  Latest over 3 years ago
  by SimbaG
• Discussion

  Embedded Components for Compact Designs

  9897 views
  0 replies
  Started over 3 years ago
  by PCBTech
• Not Answered

  How to only show page name on tabs? 0

  7696 views
  1 reply
  Latest over 3 years ago
  by Fredda