• Discussion

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  11350 views
  2 replies
  Latest over 4 years ago
  by Sugreev
• Discussion

  Error - Shape to SMD Pin spacing

  6458 views
  9 replies
  Latest over 4 years ago
  by Sugreev
• Not Answered

  Capture - Net name from port name 0

  5338 views
  3 replies
  Latest over 4 years ago
  by steve
• Discussion

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  1 reply
  Latest over 4 years ago
  by Dimo M
• Discussion

  Genus - Hierarchy Locked

  8296 views
  1 reply
  Latest over 4 years ago
  by Dimo M
• Discussion

  passing variable number of params in spectre subckt call? Locked

  12271 views
  1 reply
  Latest over 4 years ago
  by Andrew Beckett
• Discussion

  Cadence Abstract DLNOLK : Failed to get exclusive lock Locked

  12301 views
  1 reply
  Latest over 4 years ago
  by Andrew Beckett
• Discussion

  VHDL IEEE Library not recognized by RTL Compiler or Genus Locked

  16137 views
  1 reply
  Latest over 4 years ago
  by Dimo M
• Discussion

  purpose of preCTS stage & latency/skew setting Locked

  5483 views
  1 reply
  Latest over 4 years ago
  by Dimo M
• Discussion

  Organizing about "IC", "converge" "node set"... Locked

  4223 views
  4 replies
  Latest over 4 years ago
  by ichiro
• Discussion

  Add Power Ring above Core. Innovus Locked

  14332 views
  1 reply
  Latest over 4 years ago
  by Dimo M
• Not Answered

  Allegro 17.2 Desgin Entry HDL Error (SPCOCD-553) 0

  15928 views
  2 replies
  Latest over 4 years ago
  by Mohsin Hayat
• Discussion

  Editing existed PCB design

  11653 views
  4 replies
  Latest over 4 years ago
  by Sugreev
• Discussion

  use_topxp_for_sigxp command not found/ not working Locked

  10336 views
  0 replies
  Started over 4 years ago
  by AvengerThanos
• Discussion

  PCB Editor: editing lines

  15551 views
  4 replies
  Latest over 4 years ago
  by Hodgepodge