• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

×

Welcome to the Community Recognition Program!

The Community Recognition Program is a way for Cadence to recognize community participation. By sharing your real-world expertise and broadening your knowledge, you will earn points and increase your reputation.

We encourage you to give answers as well as seek answers. You’ll both expand your skill set and help others expand theirs, and that expansion will be visible and valuable to the entire community.

So, join in. Start a conversation. Ask a question. Be the reason that a question gets solved. And last but not least, don’t forget to have fun!

learn More

Cadence Community Forums

Connect with Cadence experts and users around the globe to share ideas and best practices

  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Take the Website Tour - Watch Now

CDNS Forum Categories

Browse Cadence Community Forums

Show All

OnCloud Platform

AWR Design Environment

Custom IC Design

Custom IC SKILL

PCB Design & IC Packaging (Allegro X)

System Analysis

OrCAD X

Computational Fluid Dynamics

Functional Verification

Digital Implementation

Mixed-Signal Design

Logic Design

Verification IP

RF Design

High-Level Synthesis

Implementation

PCell Designer

Functional Verification Shared Code

Hardware/Software Co-Development, Verification and Integration

RAVEL DRC Programming for IC Packaging and PCB

Community Super User Program

Want to know more? Check out this section!

Participate Now
CDNS Feature Content

Quick Links

OrCAD X—Freedom to design boldly

Unlock the Future with OrCAD X: PCB Design Simplified

Announcements

News, FAQs, and related info about how to best use the community.

Application Support and Knowledge Portal

Cadence Online Support puts the help you need within easy reach – around the clock, seven days a week

Training

Cadence helps you get the most out of your investment in our technologies through a wide range of education offerings.

Why Join?

  • Ask questions and get answers from Cadence experts
  • Share your expertise and learn from other Cadence users' experiences
  • Participate in technology- and solution-focused discussions
  • Leaderboard

    • 1
      AC202503109020
      AC202503109020 70 Points
    • 2
      avant
      avant 55 Points
    • 2
      KS202606109251
      KS202606109251 55 Points
    • 4
      HP20260601263
      HP20260601263 50 Points
    • 5
      FK202606088435
      FK202606088435 42 Points
  • Leaderboard

    • 1
      steve
      steve 17,869 Points
    • 2
      oldmouldy
      oldmouldy 13,830 Points
    • 3
      eDave
      eDave 10,381 Points
    • 4
      ShawnLogan
      ShawnLogan 9,725 Points
    • 5
      skillUser
      skillUser 7,518 Points
CDNS - feedback

Feedback, Suggestions, and Questions

Provide feedback on the forums or any other part of the site. Questions and suggestions welcome.

Latest Posts

  • Discussion

    how to stop the temp file generations in the project folder??

    Category: PCB Design

    By Dhamodharann

    •

    updated over 11 years ago by Dhamodharann

    2 replies • 16325 views
  • Discussion

    How to edit the DFA bound top & Place Bound top outlines ?

    Category: PCB Design

    By Dhamodharann

    •

    updated over 11 years ago by steve

    1 replies • 2793 views
  • Discussion

    Editing the Etch width directly in the board file is possible ?

    Category: PCB Design

    By Dhamodharann

    •

    updated over 11 years ago by steve

    1 replies • 13760 views
  • Discussion

    PTH/NPTH Drill to Copper feature spacing issue

    Category: PCB Design

    By Prapz

    •

    started over 11 years ago

    0 replies • 532 views
  • Discussion

    Labels are created in VLE while doing streaming in a GDS file.

    Category: Custom IC Design

    By RFStuff

    •

    updated over 11 years ago by Andrew Beckett

    1 replies • 14877 views
  • Discussion

    how to findout the permission of a library.

    Category: Custom IC SKILL

    By howardhaoracle

    •

    updated over 11 years ago by Andrew Beckett

    3 replies • 15772 views
  • Discussion

    Monte Carlo Analysis of I/Q amplitude and phase mismatch

    Category: RF Design

    By Sai Goutham

    •

    updated over 11 years ago by FormerMember

    1 replies • 2348 views
  • Discussion

    [Help] Tech file from cadence.

    Category: RF Design

    By Bahaa

    •

    updated over 11 years ago by Bahaa

    4 replies • 20680 views
  • Discussion

    Opening a text file in Allegro

    Category: Allegro X PCB Editor

    By eddieb1

    •

    updated over 11 years ago by Ejlersen

    10 replies • 20789 views
  • Discussion

    how to add BB Via in internal layer ??

    Category: PCB Design

    By kabalee

    •

    updated over 11 years ago by steve

    10 replies • 19233 views
<>

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2026 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information