• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

×

Welcome to the Community Recognition Program!

The Community Recognition Program is a way for Cadence to recognize community participation. By sharing your real-world expertise and broadening your knowledge, you will earn points and increase your reputation.

We encourage you to give answers as well as seek answers. You’ll both expand your skill set and help others expand theirs, and that expansion will be visible and valuable to the entire community.

So, join in. Start a conversation. Ask a question. Be the reason that a question gets solved. And last but not least, don’t forget to have fun!

learn More

Cadence Community Forums

Connect with Cadence experts and users around the globe to share ideas and best practices

  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Take the Website Tour - Watch Now

CDNS Forum Categories

Browse Cadence Community Forums

Show All

OnCloud Platform

AWR Design Environment

Custom IC Design

Custom IC SKILL

PCB Design & IC Packaging (Allegro X)

System Analysis

OrCAD X

Computational Fluid Dynamics

Functional Verification

Digital Implementation

Mixed-Signal Design

Logic Design

Verification IP

RF Design

High-Level Synthesis

Implementation

PCell Designer

Functional Verification Shared Code

Hardware/Software Co-Development, Verification and Integration

RAVEL DRC Programming for IC Packaging and PCB

Community Super User Program

Want to know more? Check out this section!

Participate Now
CDNS Feature Content

Quick Links

OrCAD X—Freedom to design boldly

Unlock the Future with OrCAD X: PCB Design Simplified

Announcements

News, FAQs, and related info about how to best use the community.

Application Support and Knowledge Portal

Cadence Online Support puts the help you need within easy reach – around the clock, seven days a week

Training

Cadence helps you get the most out of your investment in our technologies through a wide range of education offerings.

Why Join?

  • Ask questions and get answers from Cadence experts
  • Share your expertise and learn from other Cadence users' experiences
  • Participate in technology- and solution-focused discussions
  • Leaderboard

    • 1
      masamasa
      masamasa 139 Points
    • 2
      excellon1
      excellon1 127 Points
    • 3
      steve
      steve 100 Points
    • 4
      avant
      avant 76 Points
    • 5
      DavidJHutchins
      DavidJHutchins 75 Points
  • Leaderboard

    • 1
      steve
      steve 17,699 Points
    • 2
      oldmouldy
      oldmouldy 13,625 Points
    • 3
      eDave
      eDave 10,251 Points
    • 4
      ShawnLogan
      ShawnLogan 9,660 Points
    • 5
      skillUser
      skillUser 7,617 Points
CDNS - feedback

Feedback, Suggestions, and Questions

Provide feedback on the forums or any other part of the site. Questions and suggestions welcome.

Latest Posts

  • Discussion

    How to setup monte-carlo run for variation analysis in virtuoso

    Category: Custom IC Design

    By supriyo1985

    •

    updated over 1 year ago by Andrew Beckett

    1 replies • 5524 views
  • Answered

    PASS (schema) Net Custom Property from Schematic to PCB Editor

    Category: Allegro X Capture CIS

    By grax

    •

    updated over 1 year ago by grax

    2 replies • 4270 views
  • Not Answered

    PSPICE for TI - TPS2662x 60-V, 800-mA Industrial eFuse - OVP does not vary

    Category: PSpice

    By Pete2

    •

    updated over 1 year ago by Pete2

    2 replies • 1234 views
  • Answered

    EARSM Turbulence model

    Category: Turbo

    By sima101f

    •

    updated over 1 year ago by Colinda

    2 replies • 2557 views
  • Discussion

    XNOR Gate Operation Issue in Cadence

    Category: Custom IC Design

    By Maria98

    •

    updated over 1 year ago by Maria98

    2 replies • 6071 views
  • Discussion

    How to define counterbore/countersink from either top or bottom side of board?

    Category: Allegro X PCB Editor

    By PCBTech

    •

    started over 1 year ago

    0 replies • 750 views
  • Not Answered

    Incorrect plane GND with via not isolated

    Category: Allegro X PCB Editor

    By Singe

    •

    updated over 1 year ago by VVRD

    1 replies • 5161 views
  • Discussion

    Format/Syntax for Writing Aged Model Files for Reliability Simulations

    Category: Custom IC Design

    By rahulsingh

    •

    updated over 1 year ago by rahulsingh

    6 replies • 2884 views
  • Discussion

    How to make scaled prints of a layout

    Category: AWR Design Environment

    By SimTech

    •

    started over 1 year ago

    0 replies • 3654 views
  • Discussion

    [Solved] Cannot Direct Plot PAC Current (Even though it is saved in outputs!)

    Category: Custom IC Design

    By MahdiMohammadi

    •

    updated over 1 year ago by MahdiMohammadi

    2 replies • 6088 views
<>

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information