• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

×

Welcome to the Community Recognition Program!

The Community Recognition Program is a way for Cadence to recognize community participation. By sharing your real-world expertise and broadening your knowledge, you will earn points and increase your reputation.

We encourage you to give answers as well as seek answers. You’ll both expand your skill set and help others expand theirs, and that expansion will be visible and valuable to the entire community.

So, join in. Start a conversation. Ask a question. Be the reason that a question gets solved. And last but not least, don’t forget to have fun!

learn More

Cadence Community Forums

Connect with Cadence experts and users around the globe to share ideas and best practices

  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Take the Website Tour - Watch Now

CDNS Forum Categories

Browse Cadence Community Forums

Show All

OnCloud Platform

AWR Design Environment

Custom IC Design

Custom IC SKILL

PCB Design & IC Packaging (Allegro X)

System Analysis

OrCAD X

Computational Fluid Dynamics

Functional Verification

Digital Implementation

Mixed-Signal Design

Logic Design

Verification IP

RF Design

High-Level Synthesis

Implementation

PCell Designer

Functional Verification Shared Code

Hardware/Software Co-Development, Verification and Integration

RAVEL DRC Programming for IC Packaging and PCB

Community Super User Program

Want to know more? Check out this section!

Participate Now
CDNS Feature Content

Quick Links

OrCAD X—Freedom to design boldly

Unlock the Future with OrCAD X: PCB Design Simplified

Announcements

News, FAQs, and related info about how to best use the community.

Application Support and Knowledge Portal

Cadence Online Support puts the help you need within easy reach – around the clock, seven days a week

Training

Cadence helps you get the most out of your investment in our technologies through a wide range of education offerings.

Why Join?

  • Ask questions and get answers from Cadence experts
  • Share your expertise and learn from other Cadence users' experiences
  • Participate in technology- and solution-focused discussions
  • Leaderboard

    • 1
      excellon1
      excellon1 137 Points
    • 2
      masamasa
      masamasa 129 Points
    • 3
      steve
      steve 100 Points
    • 4
      DavidJHutchins
      DavidJHutchins 95 Points
    • 5
      DG202504226528
      DG202504226528 80 Points
  • Leaderboard

    • 1
      steve
      steve 17,699 Points
    • 2
      oldmouldy
      oldmouldy 13,625 Points
    • 3
      eDave
      eDave 10,251 Points
    • 4
      ShawnLogan
      ShawnLogan 9,660 Points
    • 5
      skillUser
      skillUser 7,617 Points
CDNS - feedback

Feedback, Suggestions, and Questions

Provide feedback on the forums or any other part of the site. Questions and suggestions welcome.

Latest Posts

  • Suggested Answer

    Footprint Cutout Not Updating on Layout

    Category: Allegro X PCB Editor

    By Shannonlee

    •

    updated over 2 years ago by SandeepVarrier

    4 replies • 6715 views
  • Discussion

    i want to do that kind of simulation with cadence, but i don't know how to do it ?

    Category: Custom IC Design

    By Hagar Hendy

    •

    updated over 2 years ago by ShawnLogan

    7 replies • 2991 views
  • Suggested Answer

    OrCAD Capture CIS: Export BOM via TCL

    Category: Allegro X Scripting - TCL

    By ggeorgg

    •

    updated over 2 years ago by CadAP

    5 replies • 4660 views
  • Discussion

    Sigrity Aurora solver to calculate crosstalk of parallel vias

    Category: Sigrity

    By SimTech

    •

    started over 2 years ago

    0 replies • 4298 views
  • Answered

    How do you assign multiple resistors to one library part?

    Category: Allegro X Capture CIS

    By Sky Panda

    •

    updated over 2 years ago by Sky Panda

    4 replies • 6085 views
  • Not Answered

    POSTOL and NEGTOL for Montecarlo Analysis

    Category: PSpice

    By mbrusco

    •

    updated over 2 years ago by TechiEE12

    3 replies • 5384 views
  • Discussion

    Could not find netlist procedure: _spectreCap instance

    Category: Custom IC Design

    By CJYEHRAYRAY

    •

    updated over 2 years ago by Andrew Beckett

    3 replies • 2645 views
  • Discussion

    layer cut on hierarchy

    Category: Custom IC SKILL

    By akman

    •

    updated over 2 years ago by Andrew Beckett

    5 replies • 7034 views
  • Discussion

    What are the common design rule checks you use for schematic audit?

    Category: Allegro X System Capture (EE Cockpit)

    By Krishnadas

    •

    started over 2 years ago

    0 replies • 4324 views
  • Discussion

    PDF files in library manager

    Category: Mixed-Signal Design

    By Continuum

    •

    updated over 2 years ago by Andrew Beckett

    3 replies • 6601 views
<>

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information