Custom IC Design

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Discussion

Issue with the ADE Explorer/Assembler simulator

Category: Custom IC Design

By GL202502244954

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started 16 days ago

0 replies • 173 views
Discussion

Date/time (or $system) in verilogA

Category: Custom IC Design

By leok

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updated 18 days ago by leok

2 replies • 288 views
Discussion

quantus parasitic extraction vs. SKY130 PDK

Category: Custom IC Design

By GS202507021424

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updated 19 days ago by Andrew Beckett

2 replies • 1363 views
Discussion

Quantus Error – Sky130 qrcTechFile not recognized as valid technology file

Category: Custom IC Design

By RK202509013321

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updated 19 days ago by Andrew Beckett

1 replies • 518 views
Discussion

Stop Condition of Liberate trio in characterizing a DFF

Category: Custom IC Design

By TN202507027633

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updated 22 days ago by Guangjun Cao

1 replies • 347 views
Discussion

Noise Results from Transient Noise Simulation and Noise Simulation

Category: Custom IC Design

By Kenny Lu

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updated 22 days ago by Kenny Lu

6 replies • 1013 views
Discussion

Virtuoso and Allegro Compatibility

Category: Custom IC Design

By forXTer

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updated 28 days ago by Saloni Chhabra

1 replies • 410 views
Discussion

IC25.1 Virtuoso crash but the simulation is still on going

Category: Custom IC Design

By sjwprcssw

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started 30 days ago

0 replies • 386 views
Discussion

How do you draw a parametrized layout of an inverter ?

Category: Custom IC Design

By MC20250412421

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started 1 month ago

0 replies • 327 views
Discussion

Is there any way to prevent my definition for model library from being overwritten by libInit.il of PDK while virtuoso starts up correctly?

Category: Custom IC Design

By zuiying

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updated 1 month ago by zuiying

2 replies • 594 views
Discussion

metal (or any dummy fill layer) skill code that can run at the block or chip level and automatically fill dummy metal in vacant spaces.

Category: Custom IC Design

By yogeshjaiswalCAD

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updated 1 month ago by Andrew Beckett

9 replies • 1466 views
Discussion

How to define a parameter representing a path in globel model files?

Category: Custom IC Design

By zuiying

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updated 1 month ago by Andrew Beckett

1 replies • 418 views
Discussion

Cannot generate the EMIR report using 'emirreport'

Category: Custom IC Design

By aalbason

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updated 1 month ago by Saloni Chhabra

3 replies • 720 views
Discussion

EMIR Pin Current Results Discrepancy vs Transient Simulation Results

Category: Custom IC Design

By aalbason

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started 1 month ago

0 replies • 376 views
Discussion

Re: netlisting of verilogA block with choices for prompt in CDF

Category: Custom IC Design

By SL202411208815

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started 1 month ago

0 replies • 347 views

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