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Custom IC Design

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  • Discussion

    Why doing overunder without GROW increases HPN/FPN values?

    Category: Custom IC Design

    By dummyfill

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    updated over 9 years ago by Andrew Beckett

    3 replies • 1220 views
  • Discussion

    how to overwrite veriloga code in cadence

    Category: Custom IC Design

    By black tea

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    updated over 9 years ago by Andrew Beckett

    3 replies • 14273 views
  • Discussion

    Monte Carlo simulation for device mismatch

    Category: Custom IC Design

    By sdineshkumar

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    updated over 9 years ago by Andrew Beckett

    18 replies • 28998 views
  • Discussion

    pnoise broken?

    Category: Custom IC Design

    By itos

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    started over 9 years ago

    0 replies • 13036 views
  • Discussion

    Defining a VerilogA function in C-code referring to several shared libraries

    Category: Custom IC Design

    By Herge

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    updated over 9 years ago by Herge

    1 replies • 13605 views
  • Discussion

    Large Scale Simulation

    Category: Custom IC Design

    By HS88

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    updated over 9 years ago by Andrew Beckett

    1 replies • 13523 views
  • Discussion

    SFDR in Cadence

    Category: Custom IC Design

    By black tea

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    updated over 9 years ago by Andrew Beckett

    1 replies • 14213 views
  • Discussion

    Some parameters not appearing in "vsin" source from AnalogLib

    Category: Custom IC Design

    By jdp721

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    updated over 9 years ago by jdp721

    2 replies • 3029 views
  • Discussion

    Is NeoCell a standalone product? Can it exist without Virtuoso?

    Category: Custom IC Design

    By Anonymous

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    updated over 9 years ago by Andrew Beckett

    1 replies • 13804 views
  • Discussion

    Loading corner sim results for sims run using Ocean script for Cadence IC 6.1.6

    Category: Custom IC Design

    By ag2888

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    updated over 9 years ago by Andrew Beckett

    3 replies • 14245 views
  • Discussion

    Large signal SNR with transient noise analysis

    Category: Custom IC Design

    By JoHi

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    updated over 9 years ago by JoHi

    3 replies • 15369 views
  • Discussion

    Run RCX Problems

    Category: Custom IC Design

    By rafaelon

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    updated over 9 years ago by Andrew Beckett

    1 replies • 13877 views
  • Discussion

    Verilog-A 2**integer yields wrong value

    Category: Custom IC Design

    By AlbertoGS

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    updated over 9 years ago by Andrew Beckett

    1 replies • 3893 views
  • Discussion

    ADE-XL: How to force individual result directories for each Monte Carlo point?

    Category: Custom IC Design

    By dontpanic

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    updated over 9 years ago by Andrew Beckett

    24 replies • 28329 views
  • Discussion

    What is the difference between Id and Ids notation in result browser

    Category: Custom IC Design

    By syafiq

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    updated over 9 years ago by Andrew Beckett

    1 replies • 18253 views
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