Custom IC Design

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Discussion

Verilog $random seems to be not random

Category: Custom IC Design

By HoWei

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updated over 6 years ago by Andrew Beckett

2 replies • 19053 views
Discussion

Unable to descend into any of the views defined in the view list, 'auCdl schematic'

Category: Custom IC Design

By musabfarooq

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updated over 6 years ago by Andrew Beckett

1 replies • 5424 views
Discussion

Dots instead of solid lines when plotting corners

Category: Custom IC Design

By Roman K

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updated over 6 years ago by FormerMember

1 replies • 15483 views
Discussion

Unreasonable numbers and contributors seen in ADE-L Spectre noise summary

Category: Custom IC Design

By mmVivek

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updated over 6 years ago by mmVivek

2 replies • 15122 views
Discussion

Post-Layout Simulation without front-end files of I/O cells

Category: Custom IC Design

By JavadBa

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started over 6 years ago

0 replies • 438 views
Discussion

ADE EXPLORER - use existing netlist

Category: Custom IC Design

By NickJ

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updated over 6 years ago by Frank Wiedmann

9 replies • 8458 views
Discussion

Liberate : char_library error

Category: Custom IC Design

By fengye

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updated over 6 years ago by fengye

6 replies • 16640 views
Discussion

PVS LVS Deck behaviour

Category: Custom IC Design

By Suryansh Singh

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updated over 6 years ago by Suryansh Singh

2 replies • 15324 views
Discussion

Dump a Verilog Code in Cadence Virtuso.

Category: Custom IC Design

By JAYDIP BISWAS

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updated over 6 years ago by JAYDIP BISWAS

4 replies • 14924 views
Discussion

malias function

Category: Custom IC Design

By VINCENTCHENG

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updated over 6 years ago by Andrew Beckett

3 replies • 15623 views
Discussion

CADENCE IC STUDENT VERSION/TRIAL VERSION

Category: Custom IC Design

By Thorin

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updated over 6 years ago by Anton Klotz

6 replies • 22088 views
Discussion

Cannot EDIF out

Category: Custom IC Design

By Kevinholo

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updated over 6 years ago by yankunRen

3 replies • 15208 views
Discussion

Set Subwindow ID for each Trace / Waveform

Category: Custom IC Design

By ChristophIMS

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updated over 6 years ago by Andrew Beckett

1 replies • 14229 views
Discussion

How to set a custom via as default via on VXL/GXL?

Category: Custom IC Design

By Tom Sawyer

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updated over 6 years ago by Vallabhamj

1 replies • 1383 views
Discussion

Small signal analysis during transient, triggered by event

Category: Custom IC Design

By StevenMikes

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updated over 6 years ago by StevenMikes

6 replies • 17946 views

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