Custom IC Design

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Discussion

Off-Grid pins warning in abstract generation

Category: Custom IC Design

By affaq

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updated over 15 years ago by Alex Soyer

3 replies • 14883 views
Discussion

subciruit initiated top-level current probe

Category: Custom IC Design

By Kalimero

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updated over 15 years ago by Kalimero

5 replies • 17667 views
Discussion

cadence verilog ams environment setup question

Category: Custom IC Design

By Wing2

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updated over 15 years ago by EricCDN

1 replies • 19418 views
Discussion

How to short small resistor for lvs purpose

Category: Custom IC Design

By harleyMax

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updated over 15 years ago by Andrew Beckett

7 replies • 20703 views
Discussion

Manual editing of a p2lvsfile

Category: Custom IC Design

By Slawa

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updated over 15 years ago by Slawa

6 replies • 7899 views
Discussion

How to change the Internal Cell names

Category: Custom IC Design

By sathisha

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updated over 15 years ago by Quek

1 replies • 15521 views
Discussion

ASSURA41-614: ERROR rcAddRegionTasks

Category: Custom IC Design

By tkhan

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updated over 15 years ago by Andrew Beckett

3 replies • 14366 views
Discussion

How to add PVS menu in virtuoso layout editor

Category: Custom IC Design

By shushan

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updated over 15 years ago by shushan

2 replies • 15359 views
Discussion

dose anyone know how to solve this problem???

Category: Custom IC Design

By Jay12

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updated over 15 years ago by Andrew Beckett

1 replies • 13799 views
Discussion

custum mdl functions in assertions

Category: Custom IC Design

By MarkSummers

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updated over 15 years ago by Andrew Beckett

1 replies • 14011 views
Discussion

Anyone used EQN(..) in Virtuoso-ADE->Setup Outputs?

Category: Custom IC Design

By swdesigner

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updated over 15 years ago by Andrew Beckett

2 replies • 836 views
Discussion

Techgen + RCXdspfINIT

Category: Custom IC Design

By Slawa

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updated over 15 years ago by Quek

9 replies • 9874 views
Discussion

Failed to get MPS handle

Category: Custom IC Design

By Nabavi

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updated over 15 years ago by Nabavi

4 replies • 17429 views
Discussion

tran simulation shows bad result with nport, while AC is ok

Category: Custom IC Design

By TobiasM

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updated over 15 years ago by Andrew Beckett

1 replies • 15841 views
Discussion

using nport in Verilog-AMS

Category: Custom IC Design

By TobiasM

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updated over 15 years ago by TobiasM

4 replies • 16067 views

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