Custom IC Design

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Discussion

DC run and Transient Response in Cadence ADE

Category: Custom IC Design

By FMRLI

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updated over 10 years ago by Andrew Beckett

1 replies • 14661 views
Discussion

Is it safe to ignore the checklimit warnings?

Category: Custom IC Design

By dogrush

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updated over 10 years ago by Andrew Beckett

1 replies • 15484 views
Discussion

Standard Cell Substrate Contacts

Category: Custom IC Design

By Jordan Morris

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updated over 10 years ago by Quek

1 replies • 17466 views
Discussion

Diva and Conic Sides

Category: Custom IC Design

By djca

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updated over 10 years ago by Andrew Beckett

1 replies • 14156 views
Discussion

==create Netlist fail for modified av Extracted view==

Category: Custom IC Design

By tomchen

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updated over 10 years ago by Andrew Beckett

2 replies • 15169 views
Discussion

Substrate extraction

Category: Custom IC Design

By Rade

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updated over 10 years ago by fielddev

5 replies • 17155 views
Discussion

Questions on Verilog-XL structural schematic bottom-up flow

Category: Custom IC Design

By Lynks

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started over 10 years ago

0 replies • 13483 views
Discussion

LVS versus physical Verilog from Encounter, Power Node Mismatch

Category: Custom IC Design

By Kabal

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updated over 10 years ago by Hypnus

6 replies • 17697 views
Discussion

Problem Photodiode modelling in Verilog-A

Category: Custom IC Design

By papy07

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updated over 10 years ago by ahmdd

5 replies • 16881 views
Discussion

Replacing Via1 to Via2 per Bindkey in IC5.1

Category: Custom IC Design

By Laur9

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updated over 10 years ago by Guruprasad S

11 replies • 19868 views
Discussion

Digital Pot: MOS as a logic switch

Category: Custom IC Design

By ctayers

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updated over 10 years ago by ctayers

5 replies • 16926 views
Discussion

Schematic and layout with multiple power pins

Category: Custom IC Design

By naveiitb

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updated over 10 years ago by naveiitb

4 replies • 20910 views
Discussion

Warnings for Breakdowns, not suppressing.

Category: Custom IC Design

By MarkGr15

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updated over 10 years ago by Andrew Beckett

4 replies • 17926 views
Discussion

How to make MIM cap model LVS clean

Category: Custom IC Design

By Casp

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updated over 10 years ago by Quek

1 replies • 14990 views
Discussion

Assura DRC errors - UMC 90nm

Category: Custom IC Design

By GURU M

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updated over 10 years ago by Quek

5 replies • 6781 views

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