Custom IC Design

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Discussion

fail to use VAR as 'tran' analysis parameter

Category: Custom IC Design

By fatcat1206

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updated over 7 years ago by Andrew Beckett

3 replies • 4203 views
Discussion

How do you generate a layout from schematic in Virtuoso IC 6.1.5?

Category: Custom IC Design

By ernie123

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updated over 7 years ago by Andrew Beckett

3 replies • 19894 views
Discussion

how to enable to show all the simulation warnings

Category: Custom IC Design

By enzhu

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updated over 7 years ago by Andrew Beckett

1 replies • 15409 views
Discussion

Plotting across corners with internal sweep in maestro

Category: Custom IC Design

By Gabriel Puech

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updated over 7 years ago by Andrew Beckett

7 replies • 18325 views
Discussion

Custom digital placer can't use tap-cell

Category: Custom IC Design

By jsundermeyer

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updated over 7 years ago by Andrew Beckett

5 replies • 2135 views
Discussion

Export data to CSV format

Category: Custom IC Design

By CPete

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updated over 7 years ago by Andrew Beckett

21 replies • 60367 views
Discussion

ADE-XL: force re-evaluation of Matlab script edited outside Virtuoso

Category: Custom IC Design

By dontpanic

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updated over 7 years ago by dontpanic

2 replies • 14279 views
Discussion

VPS-L: vsaplot can't find "design.info" file

Category: Custom IC Design

By KurtKimber1

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started over 7 years ago

0 replies • 445 views
Discussion

Strange problem when working with small currents in ADE L

Category: Custom IC Design

By dpalomeq

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updated over 7 years ago by dpalomeq

4 replies • 15247 views
Discussion

set parameter in definition files of adexl but given error of variable not defined (monte carlo simulation)

Category: Custom IC Design

By monglebest

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updated over 7 years ago by Andrew Beckett

5 replies • 17877 views
Discussion

ADE-XL: possible to change binding of "Open Terminal" button (launch xterm)?

Category: Custom IC Design

By dontpanic

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updated over 7 years ago by dontpanic

2 replies • 3495 views
Discussion

how to set a bindkey to display multiple layers ?

Category: Custom IC Design

By Nhumai

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updated over 7 years ago by Andrew Beckett

8 replies • 21448 views
Discussion

Monte Carlo for Verilog A based model file

Category: Custom IC Design

By Shobhitkareer

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updated over 7 years ago by Shobhitkareer

2 replies • 15143 views
Discussion

Preventing a stupid schematic mistake with NMOS back-gates

Category: Custom IC Design

By CADcasualty

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updated over 7 years ago by CADcasualty

3 replies • 16908 views
Discussion

Create a symbol from layout

Category: Custom IC Design

By Sinochka

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updated over 7 years ago by Sinochka

13 replies • 28020 views

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