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Custom IC Design

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  • Discussion

    How to verify custom design efficiently?

    Category: Custom IC Design

    By dogrush

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    updated over 10 years ago by Andrew Beckett

    1 replies • 13577 views
  • Discussion

    [Layout QUESTION] Join Transistors shared drains

    Category: Custom IC Design

    By gonsays1

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    updated over 10 years ago by Andrew Beckett

    1 replies • 19102 views
  • Discussion

    irun ams flow -- error from spectre model

    Category: Custom IC Design

    By Steven Mikes

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    updated over 10 years ago by Andrew Beckett

    1 replies • 1312 views
  • Discussion

    spectre captab does not show all nodes

    Category: Custom IC Design

    By itos

    $usertype

    •

    updated over 10 years ago by Andrew Beckett

    1 replies • 14125 views
  • Discussion

    identify every instance in netlist from Layout

    Category: Custom IC Design

    By Varun Gupta

    $usertype

    •

    updated over 10 years ago by Andrew Beckett

    1 replies • 14177 views
  • Discussion

    Device Checking, how to exclude one sub-circuit

    Category: Custom IC Design

    By Derek WANG

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    •

    updated over 10 years ago by Andrew Beckett

    1 replies • 14192 views
  • Discussion

    How to interpret (monte carlo simulation)?

    Category: Custom IC Design

    By pitter

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    •

    updated over 10 years ago by Andrew Beckett

    5 replies • 15075 views
  • Discussion

    cdsServIpc - ERROR (cmms-1889): Unknown switch '-c'

    Category: Custom IC Design

    By Karzo

    $usertype

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    updated over 10 years ago by Andrew Beckett

    1 replies • 2834 views
  • Discussion

    Problem with importing verilog to Cadence virtuoso

    Category: Custom IC Design

    By aamn

    $usertype

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    updated over 10 years ago by Andrew Beckett

    2 replies • 15563 views
  • Discussion

    Can I use a "not synthesized verilog file" in Cadence Virtuoso?

    Category: Custom IC Design

    By aamn

    $usertype

    •

    updated over 10 years ago by Andrew Beckett

    1 replies • 1185 views
  • Discussion

    How to perform a DOE (Design of Experiment) in Cadence?

    Category: Custom IC Design

    By Pyroblast

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    updated over 10 years ago by Andrew Beckett

    2 replies • 14310 views
  • Discussion

    Virtuoso AnalogEnvironment : netlisting without ocean

    Category: Custom IC Design

    By samung

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    •

    updated over 10 years ago by Andrew Beckett

    1 replies • 13621 views
  • Discussion

    Monte-Carlo simulation finish anormally

    Category: Custom IC Design

    By UUinfini

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    •

    updated over 10 years ago by Andrew Beckett

    1 replies • 13483 views
  • Discussion

    Batch run of ADE simulations using skill

    Category: Custom IC Design

    By pshan

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    •

    started over 10 years ago

    0 replies • 14122 views
  • Discussion

    Reliability study: Spectre vs Relxpert

    Category: Custom IC Design

    By Gurunath Kadam

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    •

    updated over 10 years ago by Gurunath Kadam

    1 replies • 15138 views
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