Custom IC Design

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Discussion

ADE-XL: force re-evaluation of Matlab script edited outside Virtuoso

Category: Custom IC Design

By dontpanic

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updated over 7 years ago by dontpanic

2 replies • 14542 views
Discussion

VPS-L: vsaplot can't find "design.info" file

Category: Custom IC Design

By KurtKimber1

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started over 7 years ago

0 replies • 466 views
Discussion

Strange problem when working with small currents in ADE L

Category: Custom IC Design

By dpalomeq

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updated over 7 years ago by dpalomeq

4 replies • 15554 views
Discussion

set parameter in definition files of adexl but given error of variable not defined (monte carlo simulation)

Category: Custom IC Design

By monglebest

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updated over 7 years ago by Andrew Beckett

5 replies • 18199 views
Discussion

ADE-XL: possible to change binding of "Open Terminal" button (launch xterm)?

Category: Custom IC Design

By dontpanic

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updated over 7 years ago by dontpanic

2 replies • 3588 views
Discussion

how to set a bindkey to display multiple layers ?

Category: Custom IC Design

By Nhumai

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updated over 7 years ago by Andrew Beckett

8 replies • 21814 views
Discussion

Monte Carlo for Verilog A based model file

Category: Custom IC Design

By Shobhitkareer

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updated over 7 years ago by Shobhitkareer

2 replies • 15440 views
Discussion

Preventing a stupid schematic mistake with NMOS back-gates

Category: Custom IC Design

By CADcasualty

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updated over 7 years ago by CADcasualty

3 replies • 17248 views
Discussion

Create a symbol from layout

Category: Custom IC Design

By Sinochka

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updated over 7 years ago by Sinochka

13 replies • 28585 views
Discussion

Include CDF callback parameters in netlist

Category: Custom IC Design

By Jan Cools

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updated over 7 years ago by Andrew Beckett

1 replies • 15513 views
Discussion

Assura selected rule checking

Category: Custom IC Design

By VaibhavAR

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updated over 7 years ago by Quek

4 replies • 14968 views
Discussion

CDL import with SpiceIn: W + L wrong!

Category: Custom IC Design

By bdjones1

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updated over 7 years ago by Andrew Beckett

4 replies • 21074 views
Discussion

Verilog A to symbol

Category: Custom IC Design

By Shobhitkareer

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updated over 7 years ago by Andrew Beckett

19 replies • 27210 views
Discussion

Multiple flight wires to symbol terminal

Category: Custom IC Design

By alecadair

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updated over 7 years ago by Andrew Beckett

3 replies • 16123 views
Discussion

Difference between V(P1,T1) <+ 0; and V(P1) <+ V(T1); in verilog A when they are used in 'if -else statement'

Category: Custom IC Design

By KiranTej

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updated over 7 years ago by Andrew Beckett

11 replies • 9983 views

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