Custom IC Design

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A stochastic model in Verilog A for Monte Carlo simulation

Category: Custom IC Design

By UUinfini

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updated over 11 years ago by UUinfini

29 replies • 36382 views
Discussion

Simulator Inaccuracy?

Category: Custom IC Design

By MTP3

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updated over 11 years ago by MTP3

1 replies • 13386 views
Discussion

Transient Simulation 1/f noise

Category: Custom IC Design

By kangjh7

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updated over 11 years ago by Andrew Beckett

3 replies • 2944 views
Discussion

Layout toolbox will not start with new techfile

Category: Custom IC Design

By slbecker

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updated over 11 years ago by Quek

3 replies • 15024 views
Discussion

Changes to option form do not take effect immediately - Virtuoso

Category: Custom IC Design

By mikewu216

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updated over 11 years ago by Andrew Beckett

1 replies • 1040 views
Discussion

Parameterizing a Parameterized symbol

Category: Custom IC Design

By RFStuff

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updated over 11 years ago by Andrew Beckett

1 replies • 14455 views
Discussion

Error while doing Calibre PEX

Category: Custom IC Design

By narendra046

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updated over 11 years ago by Andrew Beckett

1 replies • 20405 views
Discussion

Stream out to ascii dump file supported in Virtuoso 6.1.5?

Category: Custom IC Design

By layoutBoy

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updated over 11 years ago by layoutBoy

2 replies • 14832 views
Discussion

import a GDS file into virtuoso

Category: Custom IC Design

By Graphene1

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updated over 11 years ago by Andrew Beckett

19 replies • 44029 views
Discussion

Plotting device parameters from a PSS simulation

Category: Custom IC Design

By Desgn

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updated over 11 years ago by Andrew Beckett

1 replies • 14021 views
Discussion

Netlist procedure

Category: Custom IC Design

By pdda

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updated over 11 years ago by Andrew Beckett

1 replies • 16550 views
Discussion

[Spectre] Multiple spectre instances compiling Ahdl behavioral components

Category: Custom IC Design

By fgarcia

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updated over 11 years ago by Frank Wiedmann

4 replies • 15472 views
Discussion

Random DC voltage source generation

Category: Custom IC Design

By Tanvir100

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updated over 11 years ago by Frank Wiedmann

3 replies • 17780 views
Discussion

Accessing C code generated from veriloga compile

Category: Custom IC Design

By RobinCommander

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updated over 11 years ago by Andrew Beckett

1 replies • 13712 views
Discussion

LVS Problem running Fedora 19

Category: Custom IC Design

By ziikzak

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updated over 11 years ago by Andrew Beckett

14 replies • 18219 views

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