Custom IC Design

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Discussion

How to use calculator in ADE Explorer

Category: Custom IC Design

By SpiceMonkey

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updated over 3 years ago by SpiceMonkey

2 replies • 14172 views
Discussion

LVS complaining about lower level hierarchal design

Category: Custom IC Design

By Senan

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started over 3 years ago

0 replies • 8724 views
Discussion

PVS requires pin Label to pass the LVS

Category: Custom IC Design

By Senan

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updated over 3 years ago by Senan

2 replies • 10409 views
Discussion

PDK automation system

Category: Custom IC Design

By hustyzw

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updated over 3 years ago by Andrew Beckett

1 replies • 9848 views
Discussion

ADE Explorer Checks/Asserts Skip Device Inside Subckt is giving an error

Category: Custom IC Design

By Nader Fathy

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updated over 3 years ago by Nader Fathy

3 replies • 3870 views
Discussion

Using sampled pxf analysis to simulate deterministic jitter

Category: Custom IC Design

By Frank Wiedmann

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started over 3 years ago

0 replies • 10365 views
Discussion

via array justification?

Category: Custom IC Design

By kenc184

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updated over 3 years ago by Andrew Beckett

3 replies • 10166 views
Discussion

probing internal bus

Category: Custom IC Design

By delgsy

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updated over 3 years ago by FormerMember

3 replies • 12814 views
Discussion

Incomplete DRC Results

Category: Custom IC Design

By Kevin Buck

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started over 3 years ago

0 replies • 9306 views
Discussion

Clipping layer in Layout

Category: Custom IC Design

By MichR

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updated over 3 years ago by MichR

2 replies • 10476 views
Discussion

Variables in the SPEC section of Cadence Explorer

Category: Custom IC Design

By mhkvy4

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updated over 3 years ago by mhkvy4

4 replies • 12974 views
Discussion

ADE Explorer - Extracted DSPF Netlist - Probing Transient Current

Category: Custom IC Design

By life

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updated over 3 years ago by FormerMember

1 replies • 3850 views
Discussion

Post layout transient simulation

Category: Custom IC Design

By delgsy

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updated over 3 years ago by FormerMember

2 replies • 10474 views
Discussion

Spectre/Verilog-A: how to avoid small time step issues due to @cross() event?

Category: Custom IC Design

By dontpanic

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updated over 3 years ago by jorgeluislagos

5 replies • 10018 views
Discussion

How to change pin size in an existing symbol?

Category: Custom IC Design

By StephanWeber

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updated over 3 years ago by StephanWeber

6 replies • 13888 views

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