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Custom IC Design

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  • Discussion

    cap ground signal 'gndRefNode' cannot be found while running Assura QRC

    Category: Custom IC Design

    By shushan

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    •

    updated over 13 years ago by tingsu

    6 replies • 9339 views
  • Discussion

    No width segment in QuickView layout window

    Category: Custom IC Design

    By Teru

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    •

    updated over 13 years ago by Andrew Beckett

    3 replies • 13454 views
  • Discussion

    ASSURA 3.1.6 error message

    Category: Custom IC Design

    By yoyega

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    •

    updated over 13 years ago by rrlamichhane

    7 replies • 16205 views
  • Discussion

    Translating IC6 libaries to IC5

    Category: Custom IC Design

    By gparasiliti

    $usertype

    •

    updated over 13 years ago by Andrew Beckett

    8 replies • 16474 views
  • Discussion

    Abstract generator pin step issue: no pins created

    Category: Custom IC Design

    By bjbit

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    •

    updated over 13 years ago by bjbit

    4 replies • 14966 views
  • Discussion

    probing nets in Virtuoso Schematic isn't recognized in Simvision

    Category: Custom IC Design

    By Pavel47

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    •

    updated over 13 years ago by Andrew Beckett

    1 replies • 1818 views
  • Discussion

    segment error for symbol

    Category: Custom IC Design

    By uzzy

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    •

    updated over 13 years ago by Andrew Beckett

    1 replies • 13597 views
  • Discussion

    Stream in warning

    Category: Custom IC Design

    By ARYAMVALLI

    $usertype

    •

    updated over 13 years ago by ARYAMVALLI

    2 replies • 13322 views
  • Discussion

    setenv LBS_CLUSTER_MANAGER

    Category: Custom IC Design

    By JustinTaylor86

    $usertype

    •

    updated over 13 years ago by amwygah

    13 replies • 17282 views
  • Discussion

    subc as a symbol vs. extracted view for post layout simulation

    Category: Custom IC Design

    By bnugent

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    updated over 13 years ago by tkhan

    1 replies • 13357 views
  • Discussion

    ADE L | post-layout simulation | input.scs error | missing model

    Category: Custom IC Design

    By pitter

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    •

    updated over 13 years ago by Andrew Beckett

    4 replies • 14202 views
  • Discussion

    Changing the location of job log file

    Category: Custom IC Design

    By MaK78

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    •

    updated over 13 years ago by Andrew Beckett

    1 replies • 15671 views
  • Discussion

    ViVa waveform tool

    Category: Custom IC Design

    By sohaiba

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    •

    updated over 13 years ago by Andrew Beckett

    3 replies • 14807 views
  • Discussion

    Difference between Vt_gm, Vt_sat, Vt_lin

    Category: Custom IC Design

    By JustinTaylor86

    $usertype

    •

    updated over 13 years ago by JustinTaylor86

    2 replies • 17718 views
  • Discussion

    downgrading RHEL to support IC 5141

    Category: Custom IC Design

    By knight499

    $usertype

    •

    updated over 13 years ago by Andrew Beckett

    8 replies • 15587 views
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