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Custom IC Design

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  • Discussion

    Parameterized VHDL using generics and ADE-AMS simulation

    Category: Custom IC Design

    By lperktold

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    started over 13 years ago

    0 replies • 13499 views
  • Discussion

    get first pole from PZ analysis

    Category: Custom IC Design

    By Rainer123

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    •

    updated over 13 years ago by Rainer123

    4 replies • 13814 views
  • Discussion

    Generate Clones does not work

    Category: Custom IC Design

    By tyanata

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    •

    updated over 13 years ago by tyanata

    2 replies • 14060 views
  • Discussion

    DC Match Over Corners

    Category: Custom IC Design

    By BVT1

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    •

    started over 13 years ago

    0 replies • 13250 views
  • Discussion

    How to translate netlist with subcircuits into top-level subcircuit?

    Category: Custom IC Design

    By TiNat

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    updated over 13 years ago by skillUser

    1 replies • 6469 views
  • Discussion

    Assura LVS error (cell expanded), need help debugging the error !!

    Category: Custom IC Design

    By SivaChaitanya

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    •

    updated over 13 years ago by SivaChaitanya

    1 replies • 16885 views
  • Discussion

    Howto read port currents when having multi-terminal bus ports in VerilogA ?

    Category: Custom IC Design

    By Herge

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    •

    updated over 13 years ago by Herge

    6 replies • 15825 views
  • Discussion

    How to debug VerilogA compilation when code seems to check clean but simulation aborts when compiling ?

    Category: Custom IC Design

    By Herge

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    •

    updated over 13 years ago by Herge

    3 replies • 15178 views
  • Discussion

    montecarlo simulations beetween Wmin and Wmax for mos transistors

    Category: Custom IC Design

    By inessadm

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    •

    updated over 13 years ago by inessadm

    2 replies • 13566 views
  • Discussion

    Working with tabs in virtuoso schematic editor (opus 6.1.5 - ADE L)

    Category: Custom IC Design

    By Aldo2

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    updated over 13 years ago by Aldo2

    7 replies • 4349 views
  • Discussion

    Virtuoso: "save a copy" from read-only cell in 6.1.4 but not in 6.1.5

    Category: Custom IC Design

    By StefanSL

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    updated over 13 years ago by StefanSL

    2 replies • 1234 views
  • Discussion

    automatically spacing and aligning instances in Virtuoso schematic editor

    Category: Custom IC Design

    By MOSFET

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    •

    updated over 13 years ago by Andrew Beckett

    1 replies • 17271 views
  • Discussion

    Finding the maximum after a parametric analysis with more than one variable

    Category: Custom IC Design

    By Ueue

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    •

    updated over 13 years ago by Andrew Beckett

    1 replies • 12955 views
  • Discussion

    How to do a sp simulation using the netlist created by relxpert?

    Category: Custom IC Design

    By wyliechee

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    •

    updated over 13 years ago by Andrew Beckett

    3 replies • 13199 views
  • Discussion

    Cadence session crash.

    Category: Custom IC Design

    By maskdesigner

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    •

    updated over 13 years ago by Andrew Beckett

    5 replies • 15740 views
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