Custom IC Design

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Discussion

Net Name conflict in Virtuoso XL (layout vs. schematic)

Category: Custom IC Design

By jimstuy

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updated over 15 years ago by Quek

1 replies • 15428 views
Discussion

LVS errors

Category: Custom IC Design

By tester

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updated over 15 years ago by Quek

3 replies • 13638 views
Discussion

Multiple Model Files

Category: Custom IC Design

By Karo

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updated over 15 years ago by Andrew Beckett

3 replies • 13853 views
Discussion

Using Skill to get a list of all possible layout layers

Category: Custom IC Design

By J Wilwert

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updated over 15 years ago by J Wilwert

2 replies • 14968 views
Discussion

creating datasheets with ADE-XL

Category: Custom IC Design

By vivkr

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updated over 15 years ago by Andrew Beckett

3 replies • 15520 views
Discussion

running simulations over different corners

Category: Custom IC Design

By archive

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updated over 15 years ago by Andrew Beckett

1 replies • 13297 views
Discussion

Anyone done trim-and-sim with Monte Carlo?

Category: Custom IC Design

By swdesigner

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updated over 15 years ago by MarkSummers

9 replies • 17054 views
Discussion

NLP Expression

Category: Custom IC Design

By FORCE

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started over 15 years ago

0 replies • 13651 views
Discussion

QRC vs. RCX

Category: Custom IC Design

By archive

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updated over 15 years ago by Quek

3 replies • 14941 views
Discussion

assura LVS error

Category: Custom IC Design

By tester

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updated over 15 years ago by tester

2 replies • 13480 views
Discussion

Parasitic extraction query

Category: Custom IC Design

By shankarp

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updated over 15 years ago by Quek

1 replies • 13653 views
Discussion

change the name of a net in virtuoso XL

Category: Custom IC Design

By tester

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updated over 15 years ago by tester

4 replies • 18444 views
Discussion

NCSU CDK 1.6, IC v6.1.4, and ADE simulation?

Category: Custom IC Design

By elbUtah

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updated over 15 years ago by elbUtah

2 replies • 14188 views
Discussion

EXT913 error in VirtuosoXL

Category: Custom IC Design

By tkhan

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updated over 15 years ago by tkhan

2 replies • 13171 views
Discussion

how to use "delete cell" or any block syntax to let Assura ignore bit cell?

Category: Custom IC Design

By lijulia

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updated over 15 years ago by Quek

3 replies • 2533 views

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