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Custom IC Design

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  • Discussion

    Display operating point

    Category: Custom IC Design

    By santoshvema

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    updated over 5 years ago by FormerMember

    6 replies • 25401 views
  • Discussion

    IDS,on in MOS1 model

    Category: Custom IC Design

    By LukiLeu

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    started over 5 years ago

    0 replies • 826 views
  • Discussion

    Unable to delete a net from schematic

    Category: Custom IC Design

    By sidm

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    •

    updated over 5 years ago by Andrew Beckett

    1 replies • 12475 views
  • Discussion

    matching constraint in extracted view simulation

    Category: Custom IC Design

    By PBWU

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    •

    updated over 5 years ago by Andrew Beckett

    1 replies • 13008 views
  • Discussion

    How to copy the outputs setup and the Global variables in the mastero into the ade-XL outputs setup and Global variables respectively

    Category: Custom IC Design

    By RFStuff

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    •

    updated over 5 years ago by Andrew Beckett

    3 replies • 15650 views
  • Discussion

    Re: WildCard for Spectre Save statement

    Category: Custom IC Design

    By slim15

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    updated over 5 years ago by slim15

    2 replies • 14464 views
  • Discussion

    Can you set the schematic annotations simulation results directory remotely via ocean?

    Category: Custom IC Design

    By CADcasualty

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    updated over 5 years ago by CADcasualty

    5 replies • 13899 views
  • Discussion

    ADE-L: how to add include file without using hard-coded paths

    Category: Custom IC Design

    By dontpanic

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    updated over 5 years ago by FormerMember

    3 replies • 15112 views
  • Discussion

    Accounting for physically non equipotential ground pins in LVS

    Category: Custom IC Design

    By Flat

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    •

    updated over 5 years ago by Flat

    4 replies • 16048 views
  • Discussion

    GNT library for Virtuoso

    Category: Custom IC Design

    By kevin998x

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    •

    updated over 5 years ago by Frank Wiedmann

    3 replies • 13807 views
  • Discussion

    Disable specific instances or nets within a subcell of a testbench

    Category: Custom IC Design

    By FormerMember

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    •

    updated over 5 years ago by Andrew Beckett

    4 replies • 9478 views
  • Discussion

    alter option

    Category: Custom IC Design

    By KOTB

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    •

    updated over 5 years ago by KOTB

    6 replies • 16523 views
  • Discussion

    Using $table_model in verilogA for finding current for a given temperature

    Category: Custom IC Design

    By RFStuff

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    •

    updated over 5 years ago by RFStuff

    2 replies • 13887 views
  • Discussion

    Can Liberate take encrypted spice netlist

    Category: Custom IC Design

    By KC Lee

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    •

    updated over 5 years ago by Guangjun Cao

    2 replies • 13904 views
  • Discussion

    staircase function

    Category: Custom IC Design

    By vvdb

    $usertype

    •

    updated over 5 years ago by Andrew Beckett

    1 replies • 17587 views
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