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Custom IC Design

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  • Discussion

    Temperature coefficient of capacitance by metal to substrate in QRC extraction

    Category: Custom IC Design

    By bjbit

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    updated over 13 years ago by Quek

    1 replies • 13881 views
  • Discussion

    Power calculation

    Category: Custom IC Design

    By RAJ JOHRI

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    •

    updated over 13 years ago by Quek

    1 replies • 13752 views
  • Discussion

    cap ground signal 'gndRefNode' cannot be found while running Assura QRC

    Category: Custom IC Design

    By shushan

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    •

    updated over 13 years ago by tingsu

    6 replies • 9342 views
  • Discussion

    No width segment in QuickView layout window

    Category: Custom IC Design

    By Teru

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    •

    updated over 13 years ago by Andrew Beckett

    3 replies • 13459 views
  • Discussion

    ASSURA 3.1.6 error message

    Category: Custom IC Design

    By yoyega

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    •

    updated over 13 years ago by rrlamichhane

    7 replies • 16213 views
  • Discussion

    Translating IC6 libaries to IC5

    Category: Custom IC Design

    By gparasiliti

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    •

    updated over 13 years ago by Andrew Beckett

    8 replies • 16481 views
  • Discussion

    Abstract generator pin step issue: no pins created

    Category: Custom IC Design

    By bjbit

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    •

    updated over 13 years ago by bjbit

    4 replies • 14973 views
  • Discussion

    probing nets in Virtuoso Schematic isn't recognized in Simvision

    Category: Custom IC Design

    By Pavel47

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    updated over 13 years ago by Andrew Beckett

    1 replies • 1824 views
  • Discussion

    segment error for symbol

    Category: Custom IC Design

    By uzzy

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    •

    updated over 13 years ago by Andrew Beckett

    1 replies • 13603 views
  • Discussion

    Stream in warning

    Category: Custom IC Design

    By ARYAMVALLI

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    •

    updated over 13 years ago by ARYAMVALLI

    2 replies • 13328 views
  • Discussion

    setenv LBS_CLUSTER_MANAGER

    Category: Custom IC Design

    By JustinTaylor86

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    •

    updated over 13 years ago by amwygah

    13 replies • 17293 views
  • Discussion

    subc as a symbol vs. extracted view for post layout simulation

    Category: Custom IC Design

    By bnugent

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    updated over 13 years ago by tkhan

    1 replies • 13363 views
  • Discussion

    ADE L | post-layout simulation | input.scs error | missing model

    Category: Custom IC Design

    By pitter

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    •

    updated over 13 years ago by Andrew Beckett

    4 replies • 14212 views
  • Discussion

    Changing the location of job log file

    Category: Custom IC Design

    By MaK78

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    •

    updated over 13 years ago by Andrew Beckett

    1 replies • 15676 views
  • Discussion

    ViVa waveform tool

    Category: Custom IC Design

    By sohaiba

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    •

    updated over 13 years ago by Andrew Beckett

    3 replies • 14815 views
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