Custom IC Design

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Discussion

Automatic Place and Route for a standard cell design using a single metal layer only

Category: Custom IC Design

By write2rammy
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started over 14 years ago

0 replies • 13372 views
Discussion

Is there a viewer for Spectre pwl statements out there ?

Category: Custom IC Design

By baenisch
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updated over 14 years ago by baenisch

2 replies • 13907 views
Discussion

Parametric Analysis on Multiple Cores

Category: Custom IC Design

By AndrewMac
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started over 14 years ago

0 replies • 13225 views
Discussion

Connecting multiple bits to same output bus in cadence schematic

Category: Custom IC Design

By roy83
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updated over 14 years ago by skillUser

3 replies • 16068 views
Discussion

Promblem with streamIN/OUT in nograph mode under IC.6.1.5.65

Category: Custom IC Design

By Slayer
•
updated over 14 years ago by Slayer

2 replies • 1265 views
Discussion

Export CDL netlist from two schematic view?

Category: Custom IC Design

By fqp1000y
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updated over 14 years ago by fqp1000y

4 replies • 19254 views
Discussion

Setting default selection for Virtuoso XStream Out

Category: Custom IC Design

By archive
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updated over 14 years ago by archive

2 replies • 14079 views
Discussion

Setup for a contact

Category: Custom IC Design

By J Wilwert
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updated over 14 years ago by J Wilwert

4 replies • 13762 views
Discussion

How to disable automatic histogram plot after Monte Carlo simulation?

Category: Custom IC Design

By Soner
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updated over 14 years ago by Soner

6 replies • 15461 views
Discussion

Ploting two graphs on wavescan using only 1 y-axis

Category: Custom IC Design

By r7aaex
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updated over 14 years ago by r7aaex

2 replies • 12906 views
Discussion

How to make a situation based bindkey

Category: Custom IC Design

By Amit Biswas
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updated over 14 years ago by Amit Biswas

2 replies • 12997 views
Discussion

checkHalfWidthPathSeg always enforce

Category: Custom IC Design

By linbo
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updated over 14 years ago by Andrew Beckett

5 replies • 14400 views
Discussion

Warning: HNL: for hnlInvalidInstNames "truncate" was to be mapped by the netlister

Category: Custom IC Design

By Paulux
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updated over 14 years ago by Andrew Beckett

1 replies • 1056 views
Discussion

Monte Carlo analysis: How find what parameters change?

Category: Custom IC Design

By boulot
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updated over 14 years ago by Andrew Beckett

5 replies • 14919 views
Discussion

parameter sweep in ADEGXL?

Category: Custom IC Design

By minci
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updated over 14 years ago by Andrew Beckett

1 replies • 12858 views

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