Custom IC Design

Latest Posts

Discussion

Net Name conflict in Virtuoso XL (layout vs. schematic)

Category: Custom IC Design

By jimstuy
•
updated over 15 years ago by Quek

1 replies • 15318 views
Discussion

LVS errors

Category: Custom IC Design

By tester
•
updated over 15 years ago by Quek

3 replies • 13558 views
Discussion

Multiple Model Files

Category: Custom IC Design

By Karo
•
updated over 15 years ago by Andrew Beckett

3 replies • 13766 views
Discussion

Using Skill to get a list of all possible layout layers

Category: Custom IC Design

By J Wilwert
•
updated over 15 years ago by J Wilwert

2 replies • 14872 views
Discussion

creating datasheets with ADE-XL

Category: Custom IC Design

By vivkr
•
updated over 15 years ago by Andrew Beckett

3 replies • 15434 views
Discussion

running simulations over different corners

Category: Custom IC Design

By archive
•
updated over 15 years ago by Andrew Beckett

1 replies • 13221 views
Discussion

Anyone done trim-and-sim with Monte Carlo?

Category: Custom IC Design

By swdesigner
•
updated over 15 years ago by MarkSummers

9 replies • 16943 views
Discussion

NLP Expression

Category: Custom IC Design

By FORCE
•
started over 15 years ago

0 replies • 13574 views
Discussion

QRC vs. RCX

Category: Custom IC Design

By archive
•
updated over 15 years ago by Quek

3 replies • 14837 views
Discussion

assura LVS error

Category: Custom IC Design

By tester
•
updated over 15 years ago by tester

2 replies • 13393 views
Discussion

Parasitic extraction query

Category: Custom IC Design

By shankarp
•
updated over 15 years ago by Quek

1 replies • 13576 views
Discussion

change the name of a net in virtuoso XL

Category: Custom IC Design

By tester
•
updated over 15 years ago by tester

4 replies • 18330 views
Discussion

NCSU CDK 1.6, IC v6.1.4, and ADE simulation?

Category: Custom IC Design

By elbUtah
•
updated over 15 years ago by elbUtah

2 replies • 14095 views
Discussion

EXT913 error in VirtuosoXL

Category: Custom IC Design

By tkhan
•
updated over 15 years ago by tkhan

2 replies • 13091 views
Discussion

how to use "delete cell" or any block syntax to let Assura ignore bit cell?

Category: Custom IC Design

By lijulia
•
updated over 15 years ago by Quek

3 replies • 2510 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.