Custom IC Design

Latest Posts

Discussion

VerilogA model Monte Carlo Simulation - Histogram Curve

Category: Custom IC Design

By vijaykpd

$usertype
•
updated over 7 years ago by vijaykpd

8 replies • 4469 views
Discussion

more pin name and net name checking at check and save

Category: Custom IC Design

By enzhu

$usertype
•
updated over 7 years ago by enzhu

3 replies • 14650 views
Discussion

error in checking lvs test with calibre tool

Category: Custom IC Design

By salar1991

$usertype
•
updated over 7 years ago by salar1991

2 replies • 17829 views
Discussion

ADE XL netlisting error (some schematic components are blank)

Category: Custom IC Design

By CSCNalu

$usertype
•
updated over 7 years ago by CSCNalu

5 replies • 17027 views
Discussion

Veriloga parameter expression

Category: Custom IC Design

By RobinCommander

$usertype
•
updated over 7 years ago by RobinCommander

3 replies • 18277 views
Discussion

Leakage current and Leakage power

Category: Custom IC Design

By Sanjay24

$usertype
•
updated over 7 years ago by Quek

1 replies • 14660 views
Discussion

Verilog-A model and temperature in AC-Sim

Category: Custom IC Design

By HoWei

$usertype
•
updated over 7 years ago by HoWei

3 replies • 19872 views
Discussion

Inconsistent "PSD" results between MATLAB & Cadence Calculator

Category: Custom IC Design

By Cod Liang

$usertype
•
updated over 7 years ago by Andrew Beckett

3 replies • 6408 views
Discussion

How to set conditional tests in ADEXL to avoid running tests not needed in a sequence of tests.

Category: Custom IC Design

By angcol

$usertype
•
updated over 7 years ago by angcol

4 replies • 15256 views
Discussion

Techno via construction constraint for overlapping vias

Category: Custom IC Design

By RVERP

$usertype
•
started over 7 years ago

0 replies • 13500 views
Discussion

Parametric Analysis - Random Values

Category: Custom IC Design

By vijaykpd

$usertype
•
updated over 7 years ago by vijaykpd

2 replies • 1274 views
Discussion

filter_sg in dyn_floatdcpath check

Category: Custom IC Design

By anoopvk

$usertype
•
updated over 7 years ago by Andrew Beckett

1 replies • 14020 views
Discussion

not_gate verilogA model in ahdlLib

Category: Custom IC Design

By VLSIiitm

$usertype
•
updated over 7 years ago by Andrew Beckett

3 replies • 17170 views
Discussion

Library Manager display settings

Category: Custom IC Design

By Aldo2

$usertype
•
updated over 7 years ago by Aldo2

2 replies • 15527 views
Discussion

Virtuoso ADE Explorer/Assembler problem with load balancing system (type SGE)

Category: Custom IC Design

By WojtekB

$usertype
•
updated over 7 years ago by Andrew Beckett

1 replies • 3405 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.