Custom IC Design

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Discussion

Liberate characterization of std.cells with sequential behavior

Category: Custom IC Design

By spyridoula

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updated over 10 years ago by Andrew Beckett

1 replies • 13997 views
Discussion

ADE XL always pending

Category: Custom IC Design

By Haniel93

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updated over 10 years ago by Andrew Beckett

3 replies • 18830 views
Discussion

How to verify custom design efficiently?

Category: Custom IC Design

By dogrush

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updated over 10 years ago by Andrew Beckett

1 replies • 13611 views
Discussion

[Layout QUESTION] Join Transistors shared drains

Category: Custom IC Design

By gonsays1

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updated over 10 years ago by Andrew Beckett

1 replies • 19150 views
Discussion

irun ams flow -- error from spectre model

Category: Custom IC Design

By Steven Mikes

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updated over 10 years ago by Andrew Beckett

1 replies • 1318 views
Discussion

spectre captab does not show all nodes

Category: Custom IC Design

By itos

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updated over 10 years ago by Andrew Beckett

1 replies • 14162 views
Discussion

identify every instance in netlist from Layout

Category: Custom IC Design

By Varun Gupta

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updated over 10 years ago by Andrew Beckett

1 replies • 14214 views
Discussion

Device Checking, how to exclude one sub-circuit

Category: Custom IC Design

By Derek WANG

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updated over 10 years ago by Andrew Beckett

1 replies • 14228 views
Discussion

How to interpret (monte carlo simulation)?

Category: Custom IC Design

By pitter

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updated over 10 years ago by Andrew Beckett

5 replies • 15118 views
Discussion

cdsServIpc - ERROR (cmms-1889): Unknown switch '-c'

Category: Custom IC Design

By Karzo

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updated over 10 years ago by Andrew Beckett

1 replies • 2836 views
Discussion

Problem with importing verilog to Cadence virtuoso

Category: Custom IC Design

By aamn

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updated over 10 years ago by Andrew Beckett

2 replies • 15606 views
Discussion

Can I use a "not synthesized verilog file" in Cadence Virtuoso?

Category: Custom IC Design

By aamn

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updated over 10 years ago by Andrew Beckett

1 replies • 1190 views
Discussion

How to perform a DOE (Design of Experiment) in Cadence?

Category: Custom IC Design

By Pyroblast

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updated over 10 years ago by Andrew Beckett

2 replies • 14352 views
Discussion

Virtuoso AnalogEnvironment : netlisting without ocean

Category: Custom IC Design

By samung

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updated over 10 years ago by Andrew Beckett

1 replies • 13661 views
Discussion

Monte-Carlo simulation finish anormally

Category: Custom IC Design

By UUinfini

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updated over 10 years ago by Andrew Beckett

1 replies • 13517 views

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