Custom IC Design

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Discussion

sweep variable "bs" in hb, then use VAR("bs") in output expression, not plot in ADEXL

Category: Custom IC Design

By Taoni
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updated over 11 years ago by Andrew Beckett

6 replies • 6948 views
Discussion

Strange behavior of traponly method (MMSIM/SpectreRF)

Category: Custom IC Design

By norrin
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updated over 11 years ago by Frank Wiedmann

2 replies • 11173 views
Discussion

issue with (* cds_inherited_parameter *)

Category: Custom IC Design

By Fabb
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updated over 11 years ago by Fabb

4 replies • 14322 views
Discussion

How to use calculator to process a set of curves in wavescan

Category: Custom IC Design

By bjstroll
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updated over 11 years ago by Andrew Beckett

1 replies • 15105 views
Discussion

Extraction AS/AD in Assura RCX

Category: Custom IC Design

By TiNat
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updated over 11 years ago by Andrew Beckett

1 replies • 667 views
Discussion

ocean -nograph error

Category: Custom IC Design

By nigam214
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updated over 11 years ago by Andrew Beckett

6 replies • 3439 views
Discussion

During pcell evaluation in Assura LVS, is there a way to get cellview database information ?

Category: Custom IC Design

By windowsdee
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updated over 11 years ago by Andrew Beckett

1 replies • 12833 views
Discussion

LVS on a layout imported from Encounter versus the Physical Verilog netlist

Category: Custom IC Design

By Kabal
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updated over 11 years ago by Andrew Beckett

14 replies • 23166 views
Discussion

Verilog-A parser and HSPICE

Category: Custom IC Design

By The Setlaz
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updated over 11 years ago by The Setlaz

7 replies • 15992 views
Discussion

ADE-XL graphical outputs accessed from Skill

Category: Custom IC Design

By AxelS
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updated over 11 years ago by AxelS

3 replies • 13298 views
Discussion

Transient simulation display time issue !

Category: Custom IC Design

By isazulkc
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updated over 11 years ago by isazulkc

1 replies • 13250 views
Discussion

Using layout-only (physical) instances in Virtuoso XL

Category: Custom IC Design

By Lynks
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updated over 11 years ago by Lynks

4 replies • 17506 views
Discussion

IC615 installation question

Category: Custom IC Design

By Octavian
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updated over 11 years ago by Octavian

2 replies • 14294 views
Discussion

Verilog design in Cadence

Category: Custom IC Design

By kenambo
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updated over 11 years ago by Sali

6 replies • 20434 views
Discussion

Analog-Env Sim Error

Category: Custom IC Design

By tempVar
•
updated over 11 years ago by tempVar

5 replies • 14854 views

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